Second round of submissions, deadline July 18 | Call for Speakers for RISC-V Summit China 2024

The 5th RISC-V Summit China will be grandly convened at Zhangjiang Science Hall in Shanghai from July 16 to 19, 2025. The summit will feature a main forum, 8 vertical industry sub-forums, multiple workshops, concurrent events, and a 4,500-square-meter Future Tech Exhibition Zone. Confirmed attendees include industry leaders such as Google, NVIDIA, Infineon, and Tenstorrent. We are also inviting Chinese RISC-V pioneers like Alibaba DAMO Academy, Nuclei, Zhihe Computing, and SOPHON Technology. Additional high-profile speakers are being finalized. Anticipated to draw over 1,000 on-site professionals (80% from industrial sectors) and generate 500,000+ online views through live streams and replays, this convergence will bring together more than 100 enterprises, research institutions, and open-source technology communities. To accelerate RISC-V adoption, this summit offers free admission and cordially invites global developers and enthusiasts.

Program Committee and Sub-forum Leadership Under the Program Committee, eight vertical-specific sub-forums have been established. The Program Committee collaborates with domain authority experts to conduct impartial review of submitted proposals. Artificial Intelligence Track •Chair: XIANG Xiaoyan Processor Architect, DAMO Academy Xuantie •Vice Chair: CHEN Wei Executive Vice President, Stream Computing High-Performance Computing Track • Chair: MENG Jianyi CEO of Zhihe Computing, Chief Scientist at DAMO Academy, Rotating Chair of RVEI Technical Committee •Vice Chair: XU Tao Founder & CEO, StarFive Technology Automotive Electronics Track • Chair: HU Zhenbo Founder, Nuclei •Vice Chair: HE Ning Senior Vice President & CTO, ESWIN Computing Software & Ecosystem Track •Chair: WU Yanjun Deputy Director & Chief Engineer, Institute of Software, Chinese Academy of Sciences •Vice Chair: DUAN Jiangang R&D Director, Intel Asia-Pacific R&D Ltd.; Senior Advisor, SOPIC Cutting-edge Technology Innovation Track •Chair: HAN Jun Professor, Fudan University; Director, IP & Architecture Innovation Center, National Key Lab of Integrated Chips and Systems •Vice Chair: HUANG Bo Distinguished Professor, School of Data Science and Engineering, East China Normal University Education & Talent Development Track •Chair: ZHOU Pingqiang Vice Dean & Professor (Ph.D. Supervisor), School of Information Science and Technology, ShanghaiTech University •Vice Chair: GUO Xiaojun Executive Vice Dean, School of Integrated Circuits, Shanghai Jiao Tong University EDA Track •Chair: WU Xiaozhong Vice President, Univista Industrial Software •Vice Chair: CHEN Yingren Vice President, S2C Investment & M&A Track •Chair: LIU Ying Chairperson, Shanghai Zhangjiang Hi-Tech Park Development Co., Ltd. •Vice Chairs: WANG Lin Managing Partner, Walden International FEI Fei General Manager, Shanghai Fortera Capital Key Focus Areas Given current hot topics and pain points in the RISC-V ecosystem, we recommend prioritizing submissions addressing the following themes. We also enthusiastically welcome innovative insights and groundbreaking case studies beyond these areas. Your unique contributions will help drive new momentum for RISC-V’s global evolution! ■ Artificial Intelligence Architecture Exploration of RISC-V for AI/ML Performance Optimization of AI/ML Algorithms/Operators Latest Developments in Vector/Matrix Extensions ■ High-Performance Computing RISC-V HPC/Server Ecosystem Advancements Network-on-Chip (NoC) Interconnect Technologies Updates on RVA23 Profile Implementation ■ Automotive Electronics Standardization Progress of RISC-V Automotive Platforms Functional Safety and Certification Requirements Cybersecurity Solutions Architectures ■ Software & Ecosystem Operating Systems & Virtualization Foundational Toolchains: Compilers/Debuggers, Performance Optimization Tools Scenario-Specific Core Software Libraries & Application Porting/Optimization ■ EDA System-Level Hardware Emulation Platforms Performance Modeling & Virtual Prototyping Methodologies Emerging Directions in Verification Tools ■ Frontier Technology Innovation Quantum Computing with RISC-V In-Memory Computing Architectures Future Computing Paradigms ■ Education & Talent Development RISC-V Undergraduate Curriculum and Graduate Electives Lab Course Development and Training Centers Talent Development & Industrial Ecosystem Alignment ■ Investment & M&A CSRC Policy Analysis for Semiconductor Innovations RISC-V Investment Case Studies in Strategic Sectors EDA/IP/Fabless M&A Trends Driven by RISC-V Adoption Important Dates ● Submission Opens: April 27, 2025 ● Submission Deadline: June 7, 2025 ● Acceptance Notification: June 16, 2025 ● Submit the Draft PPT: July 7, 2025 ● Presentation Materials Finalization: July 14, 2025 ● Summit Dates: July 16–19, 2025

Submission Requirements ■ All submissions must include an abstract and an extend abstract (maximum 2 pages) in PPT/PDF format. ■ Accepted presentations require finalized slides/posters submitted by the deadline. ■ Accepted abstracts, slides, and posters may be published during the event. ■Submissions must avoid marketing-oriented content; promotional activities are welcomed in designated exhibition and advertising areas. Submission Guidelines

Speech Submission Channel：https://sessionize.com/RISC-V-Summit-China