13:30 | 45' | Introduction to Memory Safety, CHERI and Alignment to RISC-V | Rober Norton-Wright Senior Design Engineer Haydn Povey Chief Executive of SCI Semiconductor |
14:15 | 45' | Introduction to Memory Safety - Responsible for 70% of Critical Vulnerabilities & Exploits | Rober Norton-Wright Senior Design Engineer Haydn Povey Chief Executive of SCI Semiconductor |
15:00 | 30' | 茶歇 | - |
15:30 | 45' | Introduction to CHERI Technology and Implementations | Rober Norton-Wright Senior Design Engineer Haydn Povey Chief Executive of SCI Semiconductor |
16:15 | 45' | Development & Implementation of Memory Safe Systems | Rober Norton-Wright Senior Design Engineer Haydn Povey Chief Executive of SCI Semiconductor |