The 4th Dishui Lake China RISC-V Industry Forum Was Successfully Held

August 19, 2024, Shanghai -- The 4th Dishui Lake China RISC-V Industry Forum (referred to as the "Dishui Lake Forum") was successfully held at the InterContinental Shanghai  Lingang.

The forum was guided by the administrative Committee of the Lingang New Area of China (Shanghai) Pilot Free Trade Zone, co-hosted by the Shanghai Open Processor Industry Innovation Center and VeriSilicon Microelectronics (Shanghai) Co., Ltd., co-organized by Shanghai Lingang Science & Technology Innovation City Economic Development Co., Ltd., and the Shanghai Integrated Circuit Industry Association, and undertaken by VeriSilicon Technology (Shanghai) Co., Ltd. and the China RISC-V Industry Alliance. The event aimed to accelerate the RISC-V ecosystem development and promote the industrialization and application innovation of RISC-V chips in China.

The forum gathered nearly 200 attendees, including government officials, industry association leaders, experts from universities and research institutions, decision-makers from RISC-V-related enterprises, and media representatives. Additionally, it attracted over 17,000 online viewers via live stream. On the day of the event, 77 original media reports were published, highlighting the forum’s significant industry impact.

At the forum, Dr. Wayne Dai, Chairman of the China RISC-V Industry Alliance (CRVIC) and Founder, Chairman, and President of VeriSilicon, delivered an opening address reviewing the domestically developed RISC-V chips promoted at previous forums and their mass production progress.

He noted that 9 out of the 10 RISC-V chips unveiled at the 3rd Dishui Lake Forum had now entered or begun mass production. Dr. Dai highlighted that the Dishui Lake Forum had been held annually for four consecutive years, with each forum showcasing 10 new cutting-egde Chinese RISC-V chips.

In September 2018, the Shanghai Integrated Circuit Industry Association recommended VeriSilicon as the founding chairman unit to establish the CRVIC. As of the end of July 2024, CRVIC has grown to include 194 members.

To protect RISC-V enterprises from patent-related challenges, CRVIC further initiated the formation of an RISC-V Patent Alliance, which currently comprises 14 member entities. This alliance is committed to building a litigation-free patent ecosystem for RISC-V technology, fostering collaborative innovation and accelerating the development of the RISC-V industry.

Wayne Dai
Chairman, China RISC-V Industry Consortium (CRVIC)
Founder, Chairman, and CEO of VeriSilicon

Wenkan Tang, Deputy Director of the Shanghai Municipal Commission of Economy and Informatization, Shiquan Peng, Deputy Director of the Administrative Committee of the Lingang New Area in China (Shanghai) Pilot Free Trade Zone, and Yiwu Guo, Secretary-General of the Shanghai Integrated Circuit Industry Association delivered opening remarks at the forum. They extended warm congratulations on the successful convening of the Dishui Lake Forum and highly commended its active role in facilitating technological exchange and cooperation, as well as accelerating the implementation of innovation-driven development strategies. Additionally, they provided specific advices for advancing Shanghai’s open-processor hardware platforms and open-source software ecosystem.

Sameer Wasson, CEO of MIPS, delivered a keynote speech titled "RISC-V: Leading Computational Innovation". He emphasized the company's commitment to driving performance advancements and technological innovation in data center and automotive markets. By adopting the open RISC-V architecture, MIPS aimed to provide developers with greater flexibility and customization capabilities.

Professor Tao Xie, Chair Professor at Peking University and Chair of AI & Machine Learning Committee of the RISC-V International , delivered a keynote speech on "RISC-V+AI: The Path Forward in an Era of Intelligent Connectivity". In his address, he emphasized that the rapid advancement of the RISC-V open-source instruction set architecture has emerged as a pivotal focus in global technological competition. This open-standard approach has proven particularly effective in fostering industry consensus through collaborative development, while simultaneously building a comprehensive global computing ecosystem.

While acknowledging NVIDIA's current dominance in AI computing through its GPU hardware and CUDA software ecosystem, he noted the industry's growing imperative to establish alternative software frameworks that can overcome CUDA's ecosystem barriers. A developing consensus suggests leveraging the inherent advantages of RISC-V AI chips by forming strategic alliances across industry and academia, jointly developing standardized AI extension instruction sets through open-source methodologies, and collaboratively creating compatible open-source AI system software stacks. This approach aims to democratize AI computing infrastructure and accelerate innovation through shared technological development. The strategy capitalizes on RISC-V's modular architecture and open nature to create a more accessible and customizable alternative to proprietary solutions.

Following the keynote speeches, Dr. Dai moderated a thought-provoking panel discussion titled "RISC-V's Development Opportunities in Edge Computing." The distinguished panel included Jiangang Duan, R&D Director of Intel Asia-Pacific Research & Development Ltd., Zhongshu Liang, R&D Director of DAMO Academy (Shanghai) Technology Co., Ltd., Jianying Peng, Secretary-General of China RISC-V Industry Alliance and CEO of Nuclei System Technology, Zhiwei Wang, Senior VP of VeriSilicon and General Manager of Custom Chip Platform Division, Keynote speaker Professor Tao Xie, and Xiaodong Zhang, Chairman of Wuzhen Institute.

The panel engaged in lively discussions on several critical industry topics. For example, the participants talked about the projected timeline for RISC-V+AI ecosystem to rival or match CUDA's scale, desired features for AI-Pads from parental perspectives, optimal pricing strategies for AI-Pad products, expected mainstream adoption timeline for RISC-V chips in automotive applications, and forecast for Chiplet-based high-end automotive-grade chips to become mainstream.

The discussion provided valuable insights into RISC-V's roadmap across multiple application domains while fostering meaningful industry dialogue. The interactive voting mechanism allowed for immediate audience participation, creating a truly engaging experience that blended expert opinions with community perspectives.

Highlights from Panel Discussion & Live Polling Results

Topic:RISC-V scalable and customizable features, and what are the implications for the CUDA ecosystem?

views of some guests:

Xie Tao: RISC-V's growth must follow a "bottom-up" approach, requiring deep cross-sector participation to drive standardization. However, establishing standards is not the end goal, but rather a means to an end. Once standards are established, major international open-source communities will organically contribute to product evolution, iteration and self-sustaining maintenance.

Xiaodong Zhang: Reflecting on successful cases where open-source ecosystems challenged proprietary ones, we observe they typically followed a "product-first, standards-later" approach. Standards born from real-world implementations tend to succeed more organically. Conversely, attempting to define standards first and then rally industry participation often proves significantly more challenging—this phenomenon warrants serious reflection.

Jiangang Duan: AI technology remains fluid and undefined, which indicates unique opportunities for RISC-V Innovation. Beyond emerging programming languages like Triton on the software front, RISC-V's integration with novel hardware architectures is now demonstrating strong application potential. However, the ultimate success of these innovations hinges on collective ecosystem development through community-wide collaboration.

Zhongshu Liang:  Delivering high-efficiency, comprehensive extended instruction interfaces and toolchain support – along with core software library adaptations – is critical for advancing high-performance AI chip development. This fundamentally enables the 'loosely-coupled' architecture paradigm for AI computing chips."

Poll: When will the RISC-V+AI ecosystem rival or match the scale of CUDA's ecosystem? (Single choice)

Results: Over 50% of on-site participants predicted that RISC-V+AI ecosystem would rival CUDA Within 5-10 years.

Topic: AI is driving transformative changes in future career landscapes, necessitating new educational approaches to adapt. From a parent's perspective, what functions should an AI-powered educational Pad have? In other words, how shall we define an AI-Pad?

Selected Panelist Perspectives:

Zhiwei Wang: Current hardware capabilities remain insufficient to meet the demands of intelligent education. To maximize the potential of AI-Pads in education, we must advance both hardware and software in parallel."

At the hardware level, we can utilize the open, flexible, and scalable RISC-V architecture to expand AI computing power. Additionally, by incorporating additional AI engines and computing units, we can meet the software's requirements for intelligent capabilities and enhance the overall solution's competitiveness. At the software level, we can support the Android operating system and improve the intelligence of application software."

Poll 1: From a parent's perspective, what functions should an AI-Pad have? (Select three)

Results: Adaptive learning plans, learning monitoring & feedback, and personalized engagement.

Poll 2: From a parent's perspective, what price range is reasonable for an AI-Pad? (Single choice)

Results: Over 60% of on-site participants believe an AI-Pad priced between ¥2,000-5,000 is reasonable.

Topic: What is the acceptance level of RISC-V among automotive companies? Should high-end automotive-grade chips be SoC single-chip or SiP based on Chiplet?

Selected Panelist Perspectives: 

Jianying Peng:  Currently, the automotive electronics industry is undergoing a major transformation. The rise of new energy vehicles (NEVs) is driving changes in electronic and electrical architectures, leading to innovation in automotive chips, with software-defined vehicle chips emerging as a key future trend. Unlike the pre-2010 era, which focused on performance upgrades (e.g., transitioning from 16-bit to 32-bit), the emphasis now has shifted to software and AI integration. Thanks to its scalability and modularity, RISC-V is well-suited for future automotive electronics, enabling adaptable chip designs across different modules.

Pull 1: When do you expect RISC-V chips to achieve widespread adoption in automobiles? (Single choice)

Results: Over 40% of on-site participants believe that RISC-V chips are expected to achieve widespread adoption in automobiles within 3 years.

Pull 2: When is chiplet-based high-end automotive-grade chips expected to become mainstream? (Single choice)

Results: Over 44% of the on-site guests believe that chiplet-based high-end automotive-grade chips are expected to become mainstream in 5–8 years.

During the product presentation session, the following companies delivered speeches and collectively unveiled 10 new locally-developed RISC-V chip products, covering a wide range of applications including AI, AR/VR, automotive, industrial automation, and IoT:

• Beijing ESWIN Computing Technology Co., Ltd.
• SpacemiT (Hangzhou) Technology Co., Ltd.
• HPMicro (Shanghai) Co., Ltd.
• Chipways (Shanghai) Co., Ltd.
• Beijing Hyseim Technology Co., Ltd.
• Hefei Hexagon Semiconductor Co., Ltd.
• Chongqing WUQi Microelectronics Co., Ltd.
• Zhuhai DiSilicon Technology Co., Ltd.
• Resnics Technologies (Shanghai) Co., Ltd.
• Shanghai Xinsheng Semiconductor Co., Ltd.

01 EIC7702X: The world's first dual-die interconnected AI SoC integrating a 64-bit RISC-V out-of-order execution CPU and a self-developed high-performance NPU.

EIC7702X is a high-performance AI SoC.

• 64-bit RISC-V processor with self-developed high-efficiency neural network computing unit.
• Full-stack floating-point computation support for accelerated generative AI models.
• Rich peripheral interfaces + advanced audio/video processing capabilities.
• Ultra-high adaptability for AIoT devices and cloud acceleration scenarios.

02 SpacemiT Key Stone K1: The world's first 8-core RISC-V AI CPU

SpacemiT Key Stone K1 is an 8-core RISC-V AI CPU with breakthrough performance

• Compliant with RVA22 Profile & 256-bit RVV 1.0 standard
• 2× SIMD parallel processing power vs. Arm Neon
• 50 KDMIPS CPU performance
• 2 TOPS AI inference capability
• 30% higher single-core performance vs. Arm Cortex-A55
• 20% better power efficiency than A55
• CPU-centric AI acceleration architecture
• Full support for mainstream edge AI ecosystems
• Capable of running all edge-side large models

03 HPM6E00 – China's first MCU with high-performance motion control & multi-protocol industrial Ethernet support

HPM6E00 has the characteristics of high-performance motion control and high real-time industrial Ethernet interconnection. It provides RISC-V dual-core, up to 3-port Gigabit Ethernet switch, supports multiple industrial Ethernet protocols and time-sensitive networks (TSN: Time-Sensitive Networking), supports 32 high-resolution PWM outputs, 16-bit ADC, & Sigma; Digital filtering, with professional encoder management module, flexible external bus and agile hardware current loop function, it has unique advantages in high-precision motion control system.

04 XL6500R series: domestic RISC-V car gauge MCU

XL6500R Automotive-Grade MCU is an RISC-V based AEC-Q100/ISO 26262 ASIL B certified solution

• 48MHz Nuclei RISC-V core
• Compliant with:

✓ AEC-Q100 Grade 1 reliability

✓ ISO 26262 ASIL B functional safety

• Rich peripheral interfaces
• Flexible clock control architecture
• Dedicated NucleiStudio IDE support
• BLDC motor control reference designs
• Package options: LQFP48/64, QFN32
• Target applications include: automotive sensors, thermal management systems, lighting control (headlights/DRLs), wiper/window/mirror actuators, and body control modules

05 IM110GW Automotive-Grade Microcontroller (MCU)

IM110GW Automotive Body Control MCU is an ISO 26262 compliant ASIL B Certified RISC-V Solution.

• CG-EDGE single-core RISC-V 32-bit IMC
• 4-stage pipeline with 100 MHz max frequency
• Integrated FPU for floating-point acceleration

06 HX77 Series: High-Performance SoC for AR/VR Applications

HX77 Series is an RISC-V Powered AR/VR SoC with immersive graphics.

• Immersive visual experience thanks to high-performance graphics processor, and multiple graphics formats and special effects.
• Advanced processing technology to demonstrate outstanding performance and cut power consumption, thereby extending the usage time of AR devices, allowing users to immerse themselves in the AR world for longer periods
• Powerful computing capability and high-speed data processing capacity to enable rapid response to user operation commands, achieving real-time image rendering and interactive feedback

07 WQ9201 – Self-Developed RISC-V High-Performance Wi-Fi 6 Chip

WQ9201 is a dual-core RISC-V Wi-Fi 6/BT combo chip with SMP Architecture.

• Wi-Fi 6 IEEE 802.11ax protocol stack for high throughput and stable reliable wireless transmission.
• Two built-in low-power RISC-V cores, used for running Bluetooth protocol stack and application layer software respectively, meeting low-power requirements.
• Wi-Fi 6 RF and baseband functions within a single chip, with performance comparable to international top-tier manufacturers.
• Reducing Wi-Fi 6 PA power consumption by 30% to 40% compared to current industry standards

08 D8219 - "Red Hare" Digital Front-End (DFE) SoC

D8219 is a fully domestic RISC-V DFE SoC with Linux-capable application processor.

• RVA22 Profile-compliant RV64 application processor (Nuclei UX900 core)
• Support for mainline Linux
• Efficient execution of specialized algorithms and heterogeneous computing power and AI models thanks to RISC-V's high scalability.
• Compatibility with customers' existing software systems and facilitates platform-based product design based on RISC-V's software ecosystem.

09 FTTR Chip: Optical Networking Chip for Smart Home FTTR Applications

Proven results with FTTR deployment:

• 30% ARPU growth
• 60% Wi-Fi speed increase
• 100% user satisfaction
• True gigabit+ experience
• Whole-home coverage; zero dead zones with optical backhaul

10 CC2560A - World's First RISC-V Based Super SIM Chip

CC2560A is a multi-interface high-security smart card chip with large capacity.

• High-performance 32-bit RISC-V secure processor core
• 16 KB instruction cache for enhanced performance

Dishui Lake Forum dedicated a special exhibition area at the venue. Leading companies and institutions, including Lingang Science and Technology Innovation City, VeriSilicon, Nuclei Technology, as well as ten featured presenting companies, showcased their cutting-edge technologies and products, drawing significant attention and fostering lively discussions among attendees.

ABOUT SOPIC

Established in September 2024 in Zhangjiang, Pudong, Shanghai, the Shanghai Open Processor Industry Innovation Center (SOPIC) is headquartered on the 15th floor of Building 1, Chuangxin Tiandi, No. 52 Jichuang Road. As a non-profit organization, it was co-founded by leading domestic semiconductor design companies including VeriSilicon, Nuclei Technology, and DAMO Academy (Shanghai).

SOPIC serves as an industrial nexus bringing together RISC-V ecosystem stakeholders, including chip designers, IP vendors, system integrators, software developers, OEMs, and top-tier research institutions, to co-develop critical generic technology platforms. By fostering open hardware architecture to accelerate open-source software ecosystems, the center drives the industrialization and commercial deployment of RISC-V technologies.

Complementing its technical mission, SOPIC partners with China's leading universities through three integrated channels: co-developing RISC-V-specific curricula, establishing joint research laboratories, and creating applied training centers. This tripartite approach systematically cultivates professionals with cross-functional RISC-V expertise, ensuring a sustainable talent pipeline to power the ecosystem's evolution.