Elective Graduate Pilot Course on RISC-V
Our industry-education collaboration project "Pilot Courses with Open Processors" aims to establish a comprehensive shared RISC-V curriculum, spanning from chip design to practical implementation. Co-developed by academic faculty and industry experts, the curriculum will provide rich course materials, diverse hands-on lab resources, and detailed teaching guides. It promotes deep collaboration among the universities in RISC-V education, fostering an ecosystem for sharing educational resources.
Since launching the project in December 2024, we have partnered with many top academic institutions across China – including Fudan University, Shanghai Jiao Tong University, Tongji University, ShanghaiTech University, Shanghai University, Tsinghua University, Peking University, Zhejiang University, University of Electronic Science and Technology of China, Xi'an Jiaotong University, and Shandong University. Together, we have developed the "RISC-V Fundamentals: Design and Practice" course, with preliminary course materials completed. The official release of the course is scheduled for July 2025.
We warmly welcome more universities to join the project!
Previous Activities
The 3ʳᵈ Session of the Pilot Program of RISC-V Graduate Elective Course Concluded Successfully
Twenty-one teachers from 14 top domestic universities, together with industry experts, revised the courseware "Introduction to RISC-V: Design and Practice".
The 2ⁿᵈ Session of the Pilot Program of the RISC-V Graduate Elective Course Was Successfully Held
The successful holding of this meeting has laid a solid foundation for the smooth launch of the RISC-V graduate elective course series.
Launch Conference for Pilot Program of the RISC-V Graduate Elective Course Was Successfully Held
The goal of this RISC-V graduate elective course pilot class is to accelerate the cultivation of professional talents in processor chips by compiling the courseware of the RISC-V graduate elective course - "Introduction to RISC-V: Design and Practice".