Main Forum Agenda
Sub-forums Agenda

Main Forum Agenda

Opening CeremonyOpening Ceremony Morning SessionMorning Session Afternoon Session (Part 1)Afternoon Session (Part 1) Afternoon Session (Part 2)Afternoon Session (Part 2)
Opening Ceremony
Moderator of the Opening Ceremony:
Wei Huang, YICAI TV Anchor, Member of Shanghai Media Group
Zhangjiang Hall
Time Title SpeakerTitle & Speaker
09:00 - 09:35 Opening Addresses (Lu Dai)
Opening Addresses (Wayne Dai)
Opening Addresses (Lu Dai)
Opening Addresses (Wayne Dai)
Lu Dai
Chairman of RISC-V International
Government Leaders
Wayne Dai
Chairman of the Summit; Chairman of Shanghai Open Source Innovation Center (SOPIC)
Ceremony
Ceremony
09:35 - 09:45 Tea Break
Tea Break
09:45 - 10:00 From ISA to Industry: Accelerating Technical Progress and RISC-V Adoption in 2025
From ISA to Industry: Accelerating Technical Progress and RISC-V Adoption in 2025
Andrea Gallo
CEO of RISC-V International
10:00 - 10:20 Open Hardware for Future Intelligence
Open Hardware for Future Intelligence
Jim Keller
CEO of Tenstorrent
Wei-Han Lien
Chief Architect, Senior Fellow of Tenstorrent
10:20 - 10:30 Towards the New: Patient Capital Empowers Technological Innovation and Industrial Development
Towards the New: Patient Capital Empowers Technological Innovation and Industrial Development
Minmin Dai
President of Shanghai State Owned Capital Investment Co., Ltd.
10:30 - 10:40 Introduction of RISC-V Eco-District
Introduction of RISC-V Eco-District
Ying Liu
Chairman of Zhangjiang High-Tech
10:40 - 11:00 Tea Break
Tea Break
Morning Session
Moderator:
Xiaoning Qi, Vice Chairman of the Summit; Vice President of Alibaba Group
Zhangjiang Hall
Time Title SpeakerTitle & Speaker
11:00 - 11:15 The State of Union
The State of Union
Krste Asanović
Chief Architect of RISC-V International
Chief Architect of SiFive
Professor Emeritus, Professor in Graduate School, U.C. Berkeley
11:15 - 12:15 Panel Discussion: RISC-V Deployment: Opportunity and Challenge
Panel Discussion: RISC-V Deployment: Opportunity and Challenge
Host:
Wayne Dai
Chairman of the Summit; Chairman of Shanghai Open Source Innovation Center (SOPIC)
Guests:
Yungang Bao
Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences
Secretary-General of China RISC-V Alliance (CRVA)
Chief Scientist of Beijing Institute of Open Source Chip
Peng Gao
Senior Vice President of SOPHGO
Ning He
Senior Vice President & CTO of ESWIN Computing
Bob Hu
Founder of Nuclei System Technology
Wei-Han Lien
Chief Architect, Senior Fellow of Tenstorrent
Jianyi Meng
CEO of Zhihe Computing
Yijun Shi
Vice President of Sanechips
Yankin Tanurhan
Senior Vice President of Engineering, Synopsys
Sherry Xu
Co-President of UniVista
Jing Yang
Vice President of RISC-V at Alibaba DAMO Academy
Patrick Yang
CTO & Director of Nanjing Qinheng
Afternoon Session (Part 1)
Moderator:
Zhangxi Tan, Vice Chairman of the Summit; Co-Director of RIOS Lab
Zhangjiang Hall
Time Title SpeakerTitle & Speaker
13:30 - 13:45 Scaling RISC-V: Embracing a Platform and Ecosystem Mindset
Scaling RISC-V: Embracing a Platform and Ecosystem Mindset
Leendert van Doorn
Senior Vice President of Qualcomm
13:45 - 14:00 Technology Driving Standardization to Build RISC-V High-Performance Applications Foundation
Technology Driving Standardization to Build RISC-V High-Performance Applications Foundation
Xiaoning Qi
Vice President of Alibaba Group
14:00 - 14:15 Observations and Reflections on the Development of the RISC-V Ecosystem
Observations and Reflections on the Development of the RISC-V Ecosystem
Yungang Bao
Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences
Secretary-General of China RISC-V Alliance (CRVA)
Chief Scientist of Beijing Institute of Open Source Chip
14:15 - 14:30 Pursuing Technological Excellence and Driving Ecosystem Prosperity through Open Collaboration
Pursuing Technological Excellence and Driving Ecosystem Prosperity through Open Collaboration
Jianyi Meng
CEO of Zhihe Computing
14:30 - 14:45 Opportunity and Architecture Research of LLM Inference over RISC-V Servers
Opportunity and Architecture Research of LLM Inference over RISC-V Servers
Yijun Shi
Vice President of Sanechips
14:45 - 15:00 Enabling RISC-V Application Processors in NVIDIA Compute Platforms
Enabling RISC-V Application Processors in NVIDIA Compute Platforms
Frans Sijstermans
Vice President of HW Engineering, NVIDIA
15:00 - 15:30 Tea Break
Tea Break
Afternoon Session (Part 2)
Moderator:
Jianying Peng, Chairman of Program Committee of the Summit; Vice Chairman of SOPIC
Zhangjiang Hall
Time Title SpeakerTitle & Speaker
15:30 - 15:45 Industry Empowerment: Innovation of RISC-V Scenario-based Solutions and Ecosystem Collaboration
Industry Empowerment: Innovation of RISC-V Scenario-based Solutions and Ecosystem Collaboration
Ning He
Senior Vice President & CTO of ESWIN Computing
15:45 - 16:00 Accelerating SoC Innovation with Synopsys RISC-V Solutions
Accelerating SoC Innovation with Synopsys RISC-V Solutions
Yankin Tanurhan
Senior Vice President of Engineering, Synopsys
16:00 - 16:15 UniVista EDA/IP Powers Chip Design under the New Circumstances
UniVista EDA/IP Powers Chip Design under the New Circumstances
Xiaozhong Wu
Vice President of UniVista
16:15 - 16:30 Deeply Rooted, Richly Rewarded: QingKe RISC-V Technological Innovation and Commercial Ecosystem
Deeply Rooted, Richly Rewarded: QingKe RISC-V Technological Innovation and Commercial Ecosystem
Patrick Yang
CTO & Director of Nanjing Qinheng
16:30 - 16:45 Accelerating the Automotive RISC-V Ecosystem for Smart Mobility - Together
Accelerating the Automotive RISC-V Ecosystem for Smart Mobility - Together
Thomas Schneid
Head of Software, Partnership & Ecosystem Management, Infineon Technologies
Linda Liu
Senior Marketing Manager, Infineon Technologies
16:45 - 17:00 Always-on, Ultra-low-power, Ultra-light, VeriSilicon's Silicon Design Platform Based on RISC-V
Always-on, Ultra-low-power, Ultra-light, VeriSilicon's Silicon Design Platform Based on RISC-V
Wiseway Wang
Executive Vice President, General Manager of Custom Silicon Platform Division, VeriSilicon
Billy Rutledge
Director of System Research, Google Research
17:00 - 17:15 The Process and Prospect of RISC-V Commercialization IP
The Process and Prospect of RISC-V Commercialization IP
Bob Hu
Founder of Nuclei System Technology

Sub-forums Agenda

AIAI HPCHPC SWSW EmbeddedEmbedded AutoAuto EDAEDA EdgeEdge InvestInvest EDUEDU
Artificial Intelligence
Host:
Xiaoyan Xiang, Processor Architect, Xuantie, DAMO AcademyWei Chen, Executive Vice President, Stream Computing; Vice Chairman, RISC-V International AI/ML SIG
7/18 9:00-17:00
Zhangjiang Hall
Time Title SpeakerTitle & Speaker
09:00 - 09:15 Understanding the RISC-V Extensions for AI Understanding the RISC-V Extensions for AI AI requires new compute functions, particularly matrix multiplication. But it is not one size fits all, and different approaches are needed depending on the use case. RISC-V international is in the process of standardizing several new extensions to cover these different uses. Some of these use the existing vector registers, some add matrix state to the processors. This talk will explain the different options and their pros & cons, when the standard is expected to be ratified and some of the considerations when implementing them into different CPUs. Understanding the RISC-V Extensions for AI Understanding the RISC-V Extensions for AI AI requires new compute functions, particularly matrix multiplication. But it is not one size fits all, and different approaches are needed depending on the use case. RISC-V international is in the process of standardizing several new extensions to cover these different uses. Some of these use the existing vector registers, some add matrix state to the processors. This talk will explain the different options and their pros & cons, when the standard is expected to be ratified and some of the considerations when implementing them into different CPUs.
Krste Asanovic
Co-Founder & Chief Architect, SiFive
09:15 - 09:30 RISC-V is AI-Native: Why the Fastest-Moving Domain Needs the Fastest-Moving Architecture Artificial intelligence evolves at an unprecedented pace: fueled by rapidly iterating models, dynamic software stacks, and increasing demands for compute efficiency. Legacy architectures are struggling to keep up. RISC-V offers an alternative: an open, modular, and highly adaptable architecture that is not merely AI-ready, but AI-native. This keynote explores how RISC-V enables custom extensions, multiple composable extensions for matrix processing, lightweight accelerators, and software-hardware co-design that match the speed of modern AI development. From zero-day software enablement on new silicon to upstream toolchain readiness, the RISC-V ecosystem is rapidly building an alternative to GPUs and established accelerators for AI. This is more than a technical roadmap: it is a call to build an open, globally inclusive AI future—together, on RISC-V. RISC-V is AI-Native: Why the Fastest-Moving Domain Needs the Fastest-Moving Architecture Artificial intelligence evolves at an unprecedented pace: fueled by rapidly iterating models, dynamic software stacks, and increasing demands for compute efficiency. Legacy architectures are struggling to keep up. RISC-V offers an alternative: an open, modular, and highly adaptable architecture that is not merely AI-ready, but AI-native. This keynote explores how RISC-V enables custom extensions, multiple composable extensions for matrix processing, lightweight accelerators, and software-hardware co-design that match the speed of modern AI development. From zero-day software enablement on new silicon to upstream toolchain readiness, the RISC-V ecosystem is rapidly building an alternative to GPUs and established accelerators for AI. This is more than a technical roadmap: it is a call to build an open, globally inclusive AI future—together, on RISC-V.
Philipp Tomsich
Chief Technologist & Founder, VRULL GmbH
Vice Chair of the Technical Steering Committee, RISC-V International
09:30 - 09:45 RISC-V AME: A Scalable Matrix Extension for AI RISC-V AME: A Scalable Matrix Extension for AI Over the past year and a half, the Attached Matrix Extension (AME) Task Group has hosted active discussion. The group is aiming to develop a matrix extension with exclusive matrix architectural state. The design of AME targets AI applications as the primary use case, aiming to provide a unified ISA for both edge and cloud applications, while allowing optimal performance under the cost constraints of the respective application scenarios. This presentation introduces recent work from the AME Task Group, including discussion topics, existing architectural proposals, and future plans. RISC-V AME: A Scalable Matrix Extension for AI RISC-V AME: A Scalable Matrix Extension for AI Over the past year and a half, the Attached Matrix Extension (AME) Task Group has hosted active discussion. The group is aiming to develop a matrix extension with exclusive matrix architectural state. The design of AME targets AI applications as the primary use case, aiming to provide a unified ISA for both edge and cloud applications, while allowing optimal performance under the cost constraints of the respective application scenarios. This presentation introduces recent work from the AME Task Group, including discussion topics, existing architectural proposals, and future plans.
Siqi Zhao
Technical Expert, Alibaba Damo Academy
Chair of the RISC-V International AME TG
09:45 - 10:00 Driving SoC Innovations for Large-Scale AI/ML with RISC-V Processors The emerging AI/ML drove the rapid growth of the semiconductor industry in the recent years. Various approaches to AI SoC have been adopted, influenced by the technologies available to SoC design teams. As AI/ML applications expand from the cloud to the edge, we anticipate a continuous surge in SoC developments in the coming years. Andes has rich experience working with AI industry leaders, from established companies to innovative startups. RISC-V processors with diverse configurations play crucial yet distinct roles in the processing elements (PEs) of large-scale AI SoCs. Design teams can select the processor(s) to complement other PE components, such as SRAM-based CIM for GEMM and specialized hardwired engines for non-linear functions.
In this talk, we will explore the use of each of the following four RISC-V processors in a PE: scalar core (without RVV instructions), vector core, vector core with custom vector instructions, and vector core with custom vector and matrix instructions. We will discuss the trade-offs among these cases and their implications on the AI software stack as well as key microarchitecture features required in each case, using Andes solutions as examples. 		Driving SoC Innovations for Large-Scale AI/ML with RISC-V Processors The emerging AI/ML drove the rapid growth of the semiconductor industry in the recent years. Various approaches to AI SoC have been adopted, influenced by the technologies available to SoC design teams. As AI/ML applications expand from the cloud to the edge, we anticipate a continuous surge in SoC developments in the coming years. Andes has rich experience working with AI industry leaders, from established companies to innovative startups. RISC-V processors with diverse configurations play crucial yet distinct roles in the processing elements (PEs) of large-scale AI SoCs. Design teams can select the processor(s) to complement other PE components, such as SRAM-based CIM for GEMM and specialized hardwired engines for non-linear functions.
In this talk, we will explore the use of each of the following four RISC-V processors in a PE: scalar core (without RVV instructions), vector core, vector core with custom vector instructions, and vector core with custom vector and matrix instructions. We will discuss the trade-offs among these cases and their implications on the AI software stack as well as key microarchitecture features required in each case, using Andes solutions as examples.
Charlie Su
President and CTO, Andes Technology
10:00 - 10:15 Configurable High-performance Interconnect Architectures to Accelerate RISC-V AI/ML and ADAS SoCs This presentation will explore the key challenges and innovative solutions in designing interconnect architectures for high-performance, RISC-V–based SoCs targeting AI/ML and ADAS applications. It will highlight critical issues such as non-traditional data flow patterns, time-sensitive arbitration, and low-latency handling requirements—viewed from an interconnect-centric perspective. The talk showcases how Arteris addresses these challenges through a highly efficient, cost-effective, and configurable approach that significantly reduces time-to-market. Furthermore, for safety-critical domains such as automotive and industrial systems, the architecture incorporates essential design considerations for functional safety and resilience—supporting compliance with standards such as ISO 26262 and related certifications. Configurable High-performance Interconnect Architectures to Accelerate RISC-V AI/ML and ADAS SoCs This presentation will explore the key challenges and innovative solutions in designing interconnect architectures for high-performance, RISC-V–based SoCs targeting AI/ML and ADAS applications. It will highlight critical issues such as non-traditional data flow patterns, time-sensitive arbitration, and low-latency handling requirements—viewed from an interconnect-centric perspective. The talk showcases how Arteris addresses these challenges through a highly efficient, cost-effective, and configurable approach that significantly reduces time-to-market. Furthermore, for safety-critical domains such as automotive and industrial systems, the architecture incorporates essential design considerations for functional safety and resilience—supporting compliance with standards such as ISO 26262 and related certifications.
Luan Hao
Chief Architect, Arteris
10:15 - 10:45 Tea Break
Tea Break
10:45 - 11:00 Technological Innovations and Applications of LLM on RISC-V Architecture Technological Innovations and Applications of LLM on RISC-V Architecture Although the performance and parameter scale of LLM continue to increase, their mainstream architectures are stabilizing, with core operators showing a convergence trend. This paper elaborates on how the hardware capabilities provided by RISC-V's RVV and AME extensions accelerate core operators at the underlying level, significantly enhancing computational efficiency. Meanwhile, the flexibility of RISC-V supports in-depth hardware-software co-optimization tailored for diverse LLM architectures. Leveraging these hardware features, the deployment and application of LLM functionalities have been achieved in the AI-NAS product. Technological Innovations and Applications of LLM on RISC-V Architecture Technological Innovations and Applications of LLM on RISC-V Architecture Although the performance and parameter scale of LLM continue to increase, their mainstream architectures are stabilizing, with core operators showing a convergence trend. This paper elaborates on how the hardware capabilities provided by RISC-V's RVV and AME extensions accelerate core operators at the underlying level, significantly enhancing computational efficiency. Meanwhile, the flexibility of RISC-V supports in-depth hardware-software co-optimization tailored for diverse LLM architectures. Leveraging these hardware features, the deployment and application of LLM functionalities have been achieved in the AI-NAS product.
Yihao Huang
Director of Solutions, Zhihe Computing
11:00 - 11:15 Nuclei AI Library: Accelerating AI Inference with RISC-V V Extension Nuclei AI Library: Accelerating AI Inference with RISC-V V Extension With the rapid development of artificial intelligence technology, AI inference tasks are gradually moving from the cloud to edge devices and embedded systems. How to achieve efficient and low-power AI computing on hardware platforms with limited resources has become an important industry challenge.
As an open-source and extensible instruction set architecture, RISC-V's flexibility and openness provide innovative solutions for AI inference applications. Based on the RISC-V architecture, Nuclei AI Library fully utilizes the Vector Extension (V extension) instruction set and customized vector extensions to efficiently accelerate AI operators. 		Nuclei AI Library: Accelerating AI Inference with RISC-V V Extension Nuclei AI Library: Accelerating AI Inference with RISC-V V Extension With the rapid development of artificial intelligence technology, AI inference tasks are gradually moving from the cloud to edge devices and embedded systems. How to achieve efficient and low-power AI computing on hardware platforms with limited resources has become an important industry challenge.
As an open-source and extensible instruction set architecture, RISC-V's flexibility and openness provide innovative solutions for AI inference applications. Based on the RISC-V architecture, Nuclei AI Library fully utilizes the Vector Extension (V extension) instruction set and customized vector extensions to efficiently accelerate AI operators.
Zhuo Shu
Senior Embedded Software Engineer, Nuclei
11:15 - 11:30 Innovation and Applications of RISC-V Chips Introduce the technical requirements for the application of RISC-V AI in edge computing scenarios, including storage characteristics, characteristics of heterogeneous computing and characteristics of AI inference. Meanwhile, the next development trend of edge computing +RISC-V was prospected. In addition, solutions such as AI boxes, acceleration cards, and AI PCS based on RISC-V technology in edge computing scenarios are also introduced, as well as how these solutions empower specific applications. It indicates that in the AI era, the combination of RISC-V and specific application scenarios has broad application prospects. Innovation and Applications of RISC-V Chips Introduce the technical requirements for the application of RISC-V AI in edge computing scenarios, including storage characteristics, characteristics of heterogeneous computing and characteristics of AI inference. Meanwhile, the next development trend of edge computing +RISC-V was prospected. In addition, solutions such as AI boxes, acceleration cards, and AI PCS based on RISC-V technology in edge computing scenarios are also introduced, as well as how these solutions empower specific applications. It indicates that in the AI era, the combination of RISC-V and specific application scenarios has broad application prospects.
Jianyu Li
Director of Market Promotion, ESWIN Computing
11:30 - 11:45 RISC-V Powered AI Innovation: Real-World Practices of Sector-Specific Intelligent Agents RISC-V Powered AI Innovation: Real-World Practices of Sector-Specific Intelligent Agents In the context of global semiconductor industry transformation and the rapid development of AI technology, the RISC-V open instruction set architecture has emerged as a key choice for AI computing infrastructure, thanks to its modular design, customizability, and low power consumption. The platform adopts a closed-loop architecture of "chip + model + platform + agent," achieving end-to-end hardware-software co-optimization from the underlying hardware to upper-layer applications. This not only ensures data security and domestic substitution, but also significantly enhances AI inference efficiency, providing an industry-replicable technological paradigm.
The intelligent agent collaboration management platform, jointly developed by Guangzhou Public Resources Trading Group and CimIC (Shim Computing), innovatively employs the RISC-V architecture as its core computing foundation. As RISC-V continues to optimize performance in AI inference, this technical approach is poised to play a pivotal role across a broader range of industry scenarios. 		RISC-V Powered AI Innovation: Real-World Practices of Sector-Specific Intelligent Agents RISC-V Powered AI Innovation: Real-World Practices of Sector-Specific Intelligent Agents In the context of global semiconductor industry transformation and the rapid development of AI technology, the RISC-V open instruction set architecture has emerged as a key choice for AI computing infrastructure, thanks to its modular design, customizability, and low power consumption. The platform adopts a closed-loop architecture of "chip + model + platform + agent," achieving end-to-end hardware-software co-optimization from the underlying hardware to upper-layer applications. This not only ensures data security and domestic substitution, but also significantly enhances AI inference efficiency, providing an industry-replicable technological paradigm.
The intelligent agent collaboration management platform, jointly developed by Guangzhou Public Resources Trading Group and CimIC (Shim Computing), innovatively employs the RISC-V architecture as its core computing foundation. As RISC-V continues to optimize performance in AI inference, this technical approach is poised to play a pivotal role across a broader range of industry scenarios.
Zhengyu Xiao
AI Application Technology Director, StreamComputing
11:45 - 12:00 XSAI: Hardware Support for Modern LLM Kernels in a CPU Paradigm XSAI: Hardware Support for Modern LLM Kernels in a CPU Paradigm The proliferation of Large Language Models (LLMs) has spurred the development of domain-specific architectures. RISC-V offers the flexibility to integrate custom hardware acceleration while maintains a standard software ecosystem. However, existing ISA-extension-based AI accelerators or AI CPUs 1) fail to preserve the programmer- friendly CPU programming paradigm and achieve high computation throughput simultaneously, 2) lack native hardware support for critical LLM primitives. This paper introduces XSAI, a RISC-V AI processor that addresses these limitations through a holistic hardware-software co-design. Our design 1) peaks at 16 TOPS/GHz for 8-bit GEMM per core, 2) preserves traditional CPU programming paradigm (e.g., no kernel-launching, with SIMD, and with OpenMP), 3) provides unprecedented L2 cache bandwidth for GEMM unit, 4) natively supports LLM-kernel-friendly primitives like asynchronous GEMM and per-group scaling factor. XSAI: Hardware Support for Modern LLM Kernels in a CPU Paradigm XSAI: Hardware Support for Modern LLM Kernels in a CPU Paradigm The proliferation of Large Language Models (LLMs) has spurred the development of domain-specific architectures. RISC-V offers the flexibility to integrate custom hardware acceleration while maintains a standard software ecosystem. However, existing ISA-extension-based AI accelerators or AI CPUs 1) fail to preserve the programmer- friendly CPU programming paradigm and achieve high computation throughput simultaneously, 2) lack native hardware support for critical LLM primitives. This paper introduces XSAI, a RISC-V AI processor that addresses these limitations through a holistic hardware-software co-design. Our design 1) peaks at 16 TOPS/GHz for 8-bit GEMM per core, 2) preserves traditional CPU programming paradigm (e.g., no kernel-launching, with SIMD, and with OpenMP), 3) provides unprecedented L2 cache bandwidth for GEMM unit, 4) natively supports LLM-kernel-friendly primitives like asynchronous GEMM and per-group scaling factor.
Yaoyang Zhou
Senior Engineer, Beijing Institute of Open Source Chip
12:00 - 13:30 Lunch
Lunch
13:30 - 13:45 Building a Scalable AI/ML Software Stack for RISC-V: From PyTorch to Deployment on SiFive Intelligence XM Platforms Building a Scalable AI/ML Software Stack for RISC-V: From PyTorch to Deployment on SiFive Intelligence XM Platforms This talk presents the SiFive AI/ML Software Stack for RISC-V, designed to enable efficient end-to-end deployment of AI models. By leveraging the IREE compiler infrastructure, the stack supports model lowering and hardware-aware optimization targeting the SiFive X390 cores and the on-chip AI matrix engine in the new XM series platform.
We will walk through real-world deployment examples to highlight the flexibility, performance, and compiler-driven design of the stack for executing modern AI workloads on open RISC-V hardware. 		Building a Scalable AI/ML Software Stack for RISC-V: From PyTorch to Deployment on SiFive Intelligence XM Platforms Building a Scalable AI/ML Software Stack for RISC-V: From PyTorch to Deployment on SiFive Intelligence XM Platforms This talk presents the SiFive AI/ML Software Stack for RISC-V, designed to enable efficient end-to-end deployment of AI models. By leveraging the IREE compiler infrastructure, the stack supports model lowering and hardware-aware optimization targeting the SiFive X390 cores and the on-chip AI matrix engine in the new XM series platform.
We will walk through real-world deployment examples to highlight the flexibility, performance, and compiler-driven design of the stack for executing modern AI workloads on open RISC-V hardware.
Phoebe Chen
Senior Engineer, SiFive
13:45 - 14:00 XuanTie LLM Model Deployment and Optimization Practices With the explosive growth of LLM, industries across the board are being reshaped by AI. The increasing diversity of AI application scenarios has led to highly differentiated compute demands, RISC-V offers advantages such as modularity and extensibility, presenting a promising alternative for fulfilling emerging AI computing requirements.
XuanTie provides a complete AI software suite: HHB, which offers comprehensive capabilities for model deployment, inference optimization, performance analysis and debugging, and integration into the AI software ecosystem. This toolchain includes a full suite of components: HHB-AICompiler (XuanTie AI compilation framework), HHB-onnxruntime (ONNX ecosystem extension), HHB-XTorch (PyTorch ecosystem extension), HHB-XTNN (inference runtime engine), and HHB-XTnnlib (high-performance operator library).
This presentation will introduce the native XuanTie PyTorch AI software stack and optimization practice in supporting large-scale model workloads. It covers the overall software stack architecture, execution flow, as well as implementation insights and optimization strategies at both the framework and operator levels. 		XuanTie LLM Model Deployment and Optimization Practices With the explosive growth of LLM, industries across the board are being reshaped by AI. The increasing diversity of AI application scenarios has led to highly differentiated compute demands, RISC-V offers advantages such as modularity and extensibility, presenting a promising alternative for fulfilling emerging AI computing requirements.
XuanTie provides a complete AI software suite: HHB, which offers comprehensive capabilities for model deployment, inference optimization, performance analysis and debugging, and integration into the AI software ecosystem. This toolchain includes a full suite of components: HHB-AICompiler (XuanTie AI compilation framework), HHB-onnxruntime (ONNX ecosystem extension), HHB-XTorch (PyTorch ecosystem extension), HHB-XTNN (inference runtime engine), and HHB-XTnnlib (high-performance operator library).
This presentation will introduce the native XuanTie PyTorch AI software stack and optimization practice in supporting large-scale model workloads. It covers the overall software stack architecture, execution flow, as well as implementation insights and optimization strategies at both the framework and operator levels.
Peng Xu
Senior Development Engineer, Alibaba DAMO Academy
14:00 - 14:15 High-Performance AI Large Model Workstation Based on RISC-V Architecture High-Performance AI Large Model Workstation Based on RISC-V Architecture This speech explores the design concepts, technical advantages, and future potential of the RISC-V high-performance AI large model workstation.
In terms of hardware, it utilizes the UltraRISC UR-DP1000 high-performance RISC-V CPU, supporting the RV64GBCH instruction set and hardware virtualization. The scalable PCIe design supports stable operation of 1-4 Stream Computing STCP920 RISC-V AI inference cards. Through software-hardware collaborative optimization, it meets the demands of AI computing.
On the software side, a private RISC-V compiler based on GCC and LLVM is provided, supporting Linux distributions with kernel versions 5.4-6.6. Adapt to RISC-V cloud-native K8s, virtualization KubeVirt, and Virt-Manager, providing both container and virtual machine solutions. Additionally, it supports the 32B DeepSeek large model.
The CPU chip holds a leading position in the XC market and the international RISC-V field, providing stable, efficient, and flexible AI computing environments for universities, research institutions, and government-enterprise clients, thus promoting the commercial application of domestically produced RISC-V AI model workstations. 		High-Performance AI Large Model Workstation Based on RISC-V Architecture High-Performance AI Large Model Workstation Based on RISC-V Architecture This speech explores the design concepts, technical advantages, and future potential of the RISC-V high-performance AI large model workstation.
In terms of hardware, it utilizes the UltraRISC UR-DP1000 high-performance RISC-V CPU, supporting the RV64GBCH instruction set and hardware virtualization. The scalable PCIe design supports stable operation of 1-4 Stream Computing STCP920 RISC-V AI inference cards. Through software-hardware collaborative optimization, it meets the demands of AI computing.
On the software side, a private RISC-V compiler based on GCC and LLVM is provided, supporting Linux distributions with kernel versions 5.4-6.6. Adapt to RISC-V cloud-native K8s, virtualization KubeVirt, and Virt-Manager, providing both container and virtual machine solutions. Additionally, it supports the 32B DeepSeek large model.
The CPU chip holds a leading position in the XC market and the international RISC-V field, providing stable, efficient, and flexible AI computing environments for universities, research institutions, and government-enterprise clients, thus promoting the commercial application of domestically produced RISC-V AI model workstations.
Yumo Yang
Technical Expert, China Telecom Research Institute
14:15 - 14:30 Optimizing Triton for RISC-V Heterogenous AI Computing Optimizing Triton for RISC-V Heterogenous AI Computing RISC-V is the de facto ISA of future AI accelerators, Triton programming language is a cross platform AI kernel programming language. It is a viable approach to solve RISC-V AI software stack complex by compiling Triton AI kernels onto RISC-V AI accelerators and make them run performantly. This talk introduces you a novel Triton compiler development by Terapines which compiles and optimizes Triton kernels onto RISC-V based heterogenous AI chips. Optimizing Triton for RISC-V Heterogenous AI Computing Optimizing Triton for RISC-V Heterogenous AI Computing RISC-V is the de facto ISA of future AI accelerators, Triton programming language is a cross platform AI kernel programming language. It is a viable approach to solve RISC-V AI software stack complex by compiling Triton AI kernels onto RISC-V AI accelerators and make them run performantly. This talk introduces you a novel Triton compiler development by Terapines which compiles and optimizes Triton kernels onto RISC-V based heterogenous AI chips.
Hualin Wu
CTO, Terapines Technology Ltd.
14:30 - 14:45 Out-of-Order RVV: Dynamic Scheduling to Boost AI Computing Efficiency Out-of-Order RVV: Dynamic Scheduling to Boost AI Computing Efficiency By analyzing the three core challenges of AI computing, this study focuses on innovative applications of RISC-V Vector Extension (RVV) in AI acceleration. RVV‘s parametric design (e.g., configurable vector length VLEN) and ISA compatibility enable efficient adaptation across diverse AI deployment scenarios - from edge IoT to cloud data centers - breaking the ecosystem lock-in of traditional proprietary architectures. The paper elaborates how out-of-order RVV implementations achieve significant AI performance gains (6.34%-30.19% on benchmark tasks) through dynamic instruction scheduling，memory access optimization，control flow management, establishing RVV as an open, flexible computing engine solution for converged development of general-purpose LLMs and edge intelligence. Out-of-Order RVV: Dynamic Scheduling to Boost AI Computing Efficiency Out-of-Order RVV: Dynamic Scheduling to Boost AI Computing Efficiency By analyzing the three core challenges of AI computing, this study focuses on innovative applications of RISC-V Vector Extension (RVV) in AI acceleration. RVV‘s parametric design (e.g., configurable vector length VLEN) and ISA compatibility enable efficient adaptation across diverse AI deployment scenarios - from edge IoT to cloud data centers - breaking the ecosystem lock-in of traditional proprietary architectures. The paper elaborates how out-of-order RVV implementations achieve significant AI performance gains (6.34%-30.19% on benchmark tasks) through dynamic instruction scheduling，memory access optimization，control flow management, establishing RVV as an open, flexible computing engine solution for converged development of general-purpose LLMs and edge intelligence.
14:45 - 15:00 Enable RISC-V-Accelerated Ray for AI Workloads Enable RISC-V-Accelerated Ray for AI Workloads RISC-V is really revolutionizing AI processors. Meantime, as being a leading open source framework for scaling AI and Python applications, Ray, https://github.com/ray-project/ray, has been adopted widely like OpneAI, in production We believe it would be worthy getting open software - Ray into open hardware - RISC-V. This will help turn out a new era of open ML/AI platform. Here I'd like to introduce my recent efforts of enabling Ray to RISC-V arch successfully, and will demonstrate this by running Ray on a real RISC-V hardware platform. I also will talk some of Ray based extensions on RISC-V to drive ML/AI innovation Enable RISC-V-Accelerated Ray for AI Workloads Enable RISC-V-Accelerated Ray for AI Workloads RISC-V is really revolutionizing AI processors. Meantime, as being a leading open source framework for scaling AI and Python applications, Ray, https://github.com/ray-project/ray, has been adopted widely like OpneAI, in production We believe it would be worthy getting open software - Ray into open hardware - RISC-V. This will help turn out a new era of open ML/AI platform. Here I'd like to introduce my recent efforts of enabling Ray to RISC-V arch successfully, and will demonstrate this by running Ray on a real RISC-V hardware platform. I also will talk some of Ray based extensions on RISC-V to drive ML/AI innovation
Tiejun Chen
RISC-V International Ambassador
15:00 - 15:30 Tea Break
Tea Break
15:30 - 15:45 Enabling Sparse Model Inference: A Micro-Kernel Aware Approach for Optimized Libraries on the RISC-V Enabling Sparse Model Inference: A Micro-Kernel Aware Approach for Optimized Libraries on the RISC-V Deploying sparse neural networks on edge devices is a major challenge. Efforts like XNNPACK's sparse primitives have shown promise, but a performance gap remains because their unstructured sparsity patterns mismatch the native micro-kernel structures of hardware accelerators.
We introduce Micro-Kernel Aware Sparsity, a hardware-software co-design approach. Our pruning strategy explicitly chooses sparse block shapes to match the micro-kernel of the RISC-V Matrix Extension, previously disclosed at RISC-V Summits. This dramatically improves hardware utilization by ensuring most operations are processed as native workloads.
Our approach is highly effective: targeting an 8x4 micro-kernel, we pruned a ResNet-50 model to 49.83% sparsity with only a ~1.15% accuracy drop, yielding an estimated ~1.5x end-to-end speedup. This work provides a blueprint for developing AI models born to be accelerated by the RISC-V Matrix Extension, translating software sparsity into hardware-native performance. 		Enabling Sparse Model Inference: A Micro-Kernel Aware Approach for Optimized Libraries on the RISC-V Enabling Sparse Model Inference: A Micro-Kernel Aware Approach for Optimized Libraries on the RISC-V Deploying sparse neural networks on edge devices is a major challenge. Efforts like XNNPACK's sparse primitives have shown promise, but a performance gap remains because their unstructured sparsity patterns mismatch the native micro-kernel structures of hardware accelerators.
We introduce Micro-Kernel Aware Sparsity, a hardware-software co-design approach. Our pruning strategy explicitly chooses sparse block shapes to match the micro-kernel of the RISC-V Matrix Extension, previously disclosed at RISC-V Summits. This dramatically improves hardware utilization by ensuring most operations are processed as native workloads.
Our approach is highly effective: targeting an 8x4 micro-kernel, we pruned a ResNet-50 model to 49.83% sparsity with only a ~1.15% accuracy drop, yielding an estimated ~1.5x end-to-end speedup. This work provides a blueprint for developing AI models born to be accelerated by the RISC-V Matrix Extension, translating software sparsity into hardware-native performance.
Heng-Kuan Lee
Deputy Director, RD-Compute Acceleration Division, Andes
15:45 - 16:00 Design and Practice of Triton Operator Compiler for RISC-V Homogeneous AI-CPU Architecture Design and Practice of Triton Operator Compiler for RISC-V Homogeneous AI-CPU Architecture Triton is an open-source programming language and compiler developed by OpenAI, designed to simplify the writing of high-performance GPU kernels. It provides a Python-like syntax and reduces the complexity of GPU programming through high-level abstractions while maintaining high performance. Currently, PyTorch can fully replace CUDA, and domestically, the FlagGems universal operator library led by BAAI is attempting to build an AI computing ecosystem independent of CUDA. There are few practical implementations of the Triton ecosystem on CPU processors. This presentation will introduce the work on accessing and optimizing Triton on a RISC-V Homogeneous AI-CPU Architecture, with the hope of building an AI programming solution on this architecture that can match the capabilities of Triton for GPGPU. Design and Practice of Triton Operator Compiler for RISC-V Homogeneous AI-CPU Architecture Design and Practice of Triton Operator Compiler for RISC-V Homogeneous AI-CPU Architecture Triton is an open-source programming language and compiler developed by OpenAI, designed to simplify the writing of high-performance GPU kernels. It provides a Python-like syntax and reduces the complexity of GPU programming through high-level abstractions while maintaining high performance. Currently, PyTorch can fully replace CUDA, and domestically, the FlagGems universal operator library led by BAAI is attempting to build an AI computing ecosystem independent of CUDA. There are few practical implementations of the Triton ecosystem on CPU processors. This presentation will introduce the work on accessing and optimizing Triton on a RISC-V Homogeneous AI-CPU Architecture, with the hope of building an AI programming solution on this architecture that can match the capabilities of Triton for GPGPU.
Jinghui Huang
AI Software Architect, SpacemiT
16:00 - 16:15 PerfXLM 2.0: New Progress in Large Model Inference Framework on RISC-V PerfXLM 2.0: New Progress in Large Model Inference Framework on RISC-V Building upon the previous RISC-V CPU porting, the large model inference framework PerfXLM now extends support to new model migrations. It has been optimized for server-grade RISC-V CPUs, leveraging RVV 1.0 (RISC-V Vector Extension) and multi-core enhancements. Additionally, the framework explores acceleration modes combining RISC-V CPUs with NPUs. PerfXLM 2.0: New Progress in Large Model Inference Framework on RISC-V PerfXLM 2.0: New Progress in Large Model Inference Framework on RISC-V Building upon the previous RISC-V CPU porting, the large model inference framework PerfXLM now extends support to new model migrations. It has been optimized for server-grade RISC-V CPUs, leveraging RVV 1.0 (RISC-V Vector Extension) and multi-core enhancements. Additionally, the framework explores acceleration modes combining RISC-V CPUs with NPUs.
Xianyi Zhang
Founder & CEO, PerfXLab; Creator & Maintainer, OpenBLAS
16:15 - 16:30 Prototyping Verification Practice Based on Xuantie Processor AI Application Scenarios The session will mainly describe key functional indicators and corresponding verification challenges of Xuantie processors in AI application scenarios, also the work of UniVista UVHS Platform in the RISC-V AI application scenario of Damo Academy's Xuantie
* Assisting the development of Xuantie processor in AI applications: In the development and construction project of Xuantie +XT Link system architecture for AI applications, UVHS is applied to improve development and verification efficiency. Through the cascading of 16 VU19P chips, it supports fast cascading compilation of 32 core processor systems, completing the entire process from RTL code compilation to board debugging in just one week.
* Improving system performance: The Xuantie +XT Link system solution has significantly improved in Dhrystone and Coremark test results, exhibiting excellent performance under the same computing power.
* High load stress testing stability: In the application scenario of Xuantie RISC-V AI, UniVista platform demonstrates excellent stability and can withstand high load stress testing, providing solid guarantees for the reliable operation of AI applications. 		Prototyping Verification Practice Based on Xuantie Processor AI Application Scenarios The session will mainly describe key functional indicators and corresponding verification challenges of Xuantie processors in AI application scenarios, also the work of UniVista UVHS Platform in the RISC-V AI application scenario of Damo Academy's Xuantie
* Assisting the development of Xuantie processor in AI applications: In the development and construction project of Xuantie +XT Link system architecture for AI applications, UVHS is applied to improve development and verification efficiency. Through the cascading of 16 VU19P chips, it supports fast cascading compilation of 32 core processor systems, completing the entire process from RTL code compilation to board debugging in just one week.
* Improving system performance: The Xuantie +XT Link system solution has significantly improved in Dhrystone and Coremark test results, exhibiting excellent performance under the same computing power.
* High load stress testing stability: In the application scenario of Xuantie RISC-V AI, UniVista platform demonstrates excellent stability and can withstand high load stress testing, providing solid guarantees for the reliable operation of AI applications.
Feng Niu
Product Sales Director, UniVista
Hui Li
Senior R&D Engineer, Alibaba DAMO Academy
16:30 - 16:45 Open-Source Operating System Empowers AI Computing on RISC-V Architecture Open-Source Operating System Empowers AI Computing on RISC-V Architecture Rapid advancements have been observed in the RISC-V architecture, particularly concerning its AI extension instruction sets and AI accelerators. Nevertheless, substantial hurdles persist in foundational software support and deep-level optimization. Utilizing an open-source operating system serves to consolidate software and hardware resources, thereby expediting software-hardware co-optimization initiatives. Consequently, this presentation details the RISC-V AI computing work conducted using the openKylin open-source operating system, encompassing a cloud-edge converged AI computing framework, AI model computational optimization, and application power consumption optimization, concluding with a summary and future outlook. Open-Source Operating System Empowers AI Computing on RISC-V Architecture Open-Source Operating System Empowers AI Computing on RISC-V Architecture Rapid advancements have been observed in the RISC-V architecture, particularly concerning its AI extension instruction sets and AI accelerators. Nevertheless, substantial hurdles persist in foundational software support and deep-level optimization. Utilizing an open-source operating system serves to consolidate software and hardware resources, thereby expediting software-hardware co-optimization initiatives. Consequently, this presentation details the RISC-V AI computing work conducted using the openKylin open-source operating system, encompassing a cloud-edge converged AI computing framework, AI model computational optimization, and application power consumption optimization, concluding with a summary and future outlook.
Wenzhu Wang
Director of the Fundamental Software Department, Haihe Laboratory of ITAI
16:45 - 17:00 OpenHarmony + AI: Driving Commercial Breakthroughs and Industrial Innovation for RISC-V Architecture OpenHarmony + AI: Driving Commercial Breakthroughs and Industrial Innovation for RISC-V Architecture The convergence of OpenHarmony and AI technologies is ushering in revolutionary commercialization opportunities and industrial transformation for RISC-V architecture. Through hardware-software co-optimization, breakthroughs in distributed computing capabilities, and lightweight AI inference frameworks, this powerful combination demonstrates tremendous potential across smart cities, intelligent office solutions, and smart healthcare applications.
Leveraging its unique advantages in integrating OpenHarmony with AI, Runkaihong is accelerating the industrial deployment of RISC-V in these sectors, thereby enhancing the global competitiveness of RISC-V architecture. While challenges remain in performance optimization and ecosystem maturation, strategic policy support, robust industry-academia-research collaboration, and active participation in international standardization efforts will enable OpenHarmony+AI to accelerate RISC-V's industrialization process and reshape the future landscape of intelligent computing. 		OpenHarmony + AI: Driving Commercial Breakthroughs and Industrial Innovation for RISC-V Architecture OpenHarmony + AI: Driving Commercial Breakthroughs and Industrial Innovation for RISC-V Architecture The convergence of OpenHarmony and AI technologies is ushering in revolutionary commercialization opportunities and industrial transformation for RISC-V architecture. Through hardware-software co-optimization, breakthroughs in distributed computing capabilities, and lightweight AI inference frameworks, this powerful combination demonstrates tremendous potential across smart cities, intelligent office solutions, and smart healthcare applications.
Leveraging its unique advantages in integrating OpenHarmony with AI, Runkaihong is accelerating the industrial deployment of RISC-V in these sectors, thereby enhancing the global competitiveness of RISC-V architecture. While challenges remain in performance optimization and ecosystem maturation, strategic policy support, robust industry-academia-research collaboration, and active participation in international standardization efforts will enable OpenHarmony+AI to accelerate RISC-V's industrialization process and reshape the future landscape of intelligent computing.
Dawu Yu
Vice President, Jiangsu Run Kaihong Digital Technology Co., Ltd.
High-Performance Computing
Host:
Jianyi Meng, CEO of Zhihe Computing, Chief Scientist at Alibaba DAMO Academy, Rotating Chair of RVEI Technical CommitteeTao Xu, Founder & CEO, StarFive Technology
7/18 9:00-17:15
Inspire Hall
Time Title SpeakerTitle & Speaker
09:00 - 09:15 From CPU to compute subsystem, to road to support high performance compure From CPU to compute subsystem, to road to support high performance compure As the world's highest-performance open-source RISC-V processor, XiangShan, the speaker will provide updates on its design and verification progress over the past year (including verification status updates for XiangShan Nanhu V5 and Kunminghu V2). This progress will also introduce the current status of XiangShan's reference design and explain the necessity for developing a computing subsystem. The presentation will then delve into the server-oriented computing subsystem and the embedded-oriented computing subsystem respectively, concluding with an introduction to the unified verification environment based on the computing subsystem. From CPU to compute subsystem, to road to support high performance compure From CPU to compute subsystem, to road to support high performance compure As the world's highest-performance open-source RISC-V processor, XiangShan, the speaker will provide updates on its design and verification progress over the past year (including verification status updates for XiangShan Nanhu V5 and Kunminghu V2). This progress will also introduce the current status of XiangShan's reference design and explain the necessity for developing a computing subsystem. The presentation will then delve into the server-oriented computing subsystem and the embedded-oriented computing subsystem respectively, concluding with an introduction to the unified verification environment based on the computing subsystem.
Jian Zhang
Product Manager, BOSC
09:15 - 09:30 XuanTie Series Processors: Continuous Innovation and Iteration RISC-V is becoming one of the three major ISAs globally. XuanTie, as one of the largest commercial RISC-V CPU IP providers in China, offers a product line covering all scenarios from low-power to high-performance. In response to the industry’s anticipation in high-performance general-purpose computing, XuanTie team officially delivered the latest flagship IP, XuanTie C930, earlier this year. Here we will walk through the architecture and microarchitecture of C930. From the pipeline's front-end instruction fetching and branch prediction, through the mid-core decoding, splitting, and OoO scheduling, to the back-end execution and high-bandwidth OoO memory access, we will comprehensively analyze the technological innovations of C930, and how they boosts the performance beyond 15 pts/GHz in specint06. Additionally, we will introduce the latest XuanTie Link, which supports building multi-core systems with C930. We will also discuss Xuantie DSA Extension Interface integrated with C930, which facilitates specific acceleration needs for users on any application. It will leverage the extensibility of RISC-V to achieve tens or hundreds of times performance increase in hot areas such as AI. XuanTie Series Processors: Continuous Innovation and Iteration RISC-V is becoming one of the three major ISAs globally. XuanTie, as one of the largest commercial RISC-V CPU IP providers in China, offers a product line covering all scenarios from low-power to high-performance. In response to the industry’s anticipation in high-performance general-purpose computing, XuanTie team officially delivered the latest flagship IP, XuanTie C930, earlier this year. Here we will walk through the architecture and microarchitecture of C930. From the pipeline's front-end instruction fetching and branch prediction, through the mid-core decoding, splitting, and OoO scheduling, to the back-end execution and high-bandwidth OoO memory access, we will comprehensively analyze the technological innovations of C930, and how they boosts the performance beyond 15 pts/GHz in specint06. Additionally, we will introduce the latest XuanTie Link, which supports building multi-core systems with C930. We will also discuss Xuantie DSA Extension Interface integrated with C930, which facilitates specific acceleration needs for users on any application. It will leverage the extensibility of RISC-V to achieve tens or hundreds of times performance increase in hot areas such as AI.
Haoyan Jia
Staff Engineer, Alibaba DAMO Academy
09:30 - 09:45 Proposal for "Leverage RISC-V for High Performance Computing"
Proposal for "Leverage RISC-V for High Performance Computing"
Frankwell Lin
Board of Director, RISC-V International
Chairman & CEO, Andes
09:45 - 10:00 Nuclei ASIL B/D RISC V IP Automotive implementation challenges and solutions The speech introduces the RISC-V CPU IP auto compliance methodology in Nuclei to achieve systematic ASIL-D and random hardware capability ASIL-B&D. The random hardware capability for different ASIL customers mainly depends on Nuclei self-developed HW/SW mechanisms. The speech also shares the challenges and solutions where Nuclei automotive customers integrate RISC-V IP to achieve automotive-grade ICs, which include Radar, Lidar, GNSS, MCU and etc. Nuclei ASIL B/D RISC V IP Automotive implementation challenges and solutions The speech introduces the RISC-V CPU IP auto compliance methodology in Nuclei to achieve systematic ASIL-D and random hardware capability ASIL-B&D. The random hardware capability for different ASIL customers mainly depends on Nuclei self-developed HW/SW mechanisms. The speech also shares the challenges and solutions where Nuclei automotive customers integrate RISC-V IP to achieve automotive-grade ICs, which include Radar, Lidar, GNSS, MCU and etc.
Nathan Ma
AVP of Marketing and Strategy, Nuclei
10:00 - 10:15 Scaling out RISC-V systems for HPC The High-Performance Computing market is experiencing significant growth, particularly driven by advancements in GPU technology and the increasing adoption of AI and machine learning. By 2030, some analysts estimate the HPC market to reach $64.6 billion, with GPUs playing a key role in this expansion. The rise of AI and machine learning workloads is driving the need for more powerful computing resources, with GPUs being well-suited for parallel processing and handling the demands of these applications.
This industry has a history of driving toward open standards. This is driving a new set of system architectures to be proposed, designed and, ultimately, deployed. The advancements inside the RISC-V ecosystem including more advanced processor implementations, extensions to the ISA and the definition of common server platforms, offer an opportunity to create highly scalable HPC systems from efficient compute cores. This presentation will review work between SiFive and Arteris to verify high core count SoCs based on RISC-V CPU cores and a CHI based interconnect. We’ll also discuss some of the learnings from this work that can be applied to building multi-die (chiplet) implementations. 		Scaling out RISC-V systems for HPC The High-Performance Computing market is experiencing significant growth, particularly driven by advancements in GPU technology and the increasing adoption of AI and machine learning. By 2030, some analysts estimate the HPC market to reach $64.6 billion, with GPUs playing a key role in this expansion. The rise of AI and machine learning workloads is driving the need for more powerful computing resources, with GPUs being well-suited for parallel processing and handling the demands of these applications.
This industry has a history of driving toward open standards. This is driving a new set of system architectures to be proposed, designed and, ultimately, deployed. The advancements inside the RISC-V ecosystem including more advanced processor implementations, extensions to the ISA and the definition of common server platforms, offer an opportunity to create highly scalable HPC systems from efficient compute cores. This presentation will review work between SiFive and Arteris to verify high core count SoCs based on RISC-V CPU cores and a CHI based interconnect. We’ll also discuss some of the learnings from this work that can be applied to building multi-die (chiplet) implementations.
Yan Zhang
Principal FAE, SiFive
Cunrong Feng
Senior FAE manager, Arteris
10:15 - 10:45 Tea Break
Tea Break
10:45 - 11:00 Practical Implementation of Coherent On-Chip Network StarNoC Integrated with RISC-V Practical Implementation of Coherent On-Chip Network StarNoC Integrated with RISC-V With the explosive growth of AI and High-Performance Computing (HPC), RISC-V SoCs face data coherence challenges in multi-core scaling, heterogeneous integration, and multi-chip interconnect. StarFive's self-developed StarNoC is China's first coherent NoC IP, supporting distributed cache coherence, flexible Ring/Mesh topologies, and parameterized configurations. Having completed verification and entered the delivery phase, StarNoC addresses the gap in domestically developed coherent NoC solutions. Practical Implementation of Coherent On-Chip Network StarNoC Integrated with RISC-V Practical Implementation of Coherent On-Chip Network StarNoC Integrated with RISC-V With the explosive growth of AI and High-Performance Computing (HPC), RISC-V SoCs face data coherence challenges in multi-core scaling, heterogeneous integration, and multi-chip interconnect. StarFive's self-developed StarNoC is China's first coherent NoC IP, supporting distributed cache coherence, flexible Ring/Mesh topologies, and parameterized configurations. Having completed verification and entered the delivery phase, StarNoC addresses the gap in domestically developed coherent NoC solutions.
Jay Zhou
General Manager of IP BU, StarFive Technology
11:00 - 11:15 UR-DP1000: A High-performance 8-core 64-bit RISC-V Microprocessor UR-DP1000 is a high-performance 64-bit general-purpose desktop-level multi-core microprocessor launched by UltraRISC Technology in March 2025. This chip is based on the RISC-V instruction set architecture, integrates 8 self-developed UR-CP100 processor cores, utilizes a 12nm process, and operates at a frequency of 2.0-2.3GHz with a TDP of 30W. Its single-core SPECint2006 and SPECfp2006 scores reach 10.4/GHz and 12.0/GHz, respectively. Compared to similar products, the UR-DP1000 demonstrates advantages in performance and power consumption. This talk details the SoC architecture of the UR-DP1000 and the microarchitecture of the UR-CP100 processor core (which supports the RV64GCBHX instruction set, employs an out-of-order 4-issue superscalar design, and supports hardware virtualization), while also introducing its benchmark performance, software ecosystem, and typical application scenarios. UR-DP1000: A High-performance 8-core 64-bit RISC-V Microprocessor UR-DP1000 is a high-performance 64-bit general-purpose desktop-level multi-core microprocessor launched by UltraRISC Technology in March 2025. This chip is based on the RISC-V instruction set architecture, integrates 8 self-developed UR-CP100 processor cores, utilizes a 12nm process, and operates at a frequency of 2.0-2.3GHz with a TDP of 30W. Its single-core SPECint2006 and SPECfp2006 scores reach 10.4/GHz and 12.0/GHz, respectively. Compared to similar products, the UR-DP1000 demonstrates advantages in performance and power consumption. This talk details the SoC architecture of the UR-DP1000 and the microarchitecture of the UR-CP100 processor core (which supports the RV64GCBHX instruction set, employs an out-of-order 4-issue superscalar design, and supports hardware virtualization), while also introducing its benchmark performance, software ecosystem, and typical application scenarios.
Jiang Jiang
Executive President and CTO, UltraRISC Technology
11:15 - 11:30 Driving Open-Source Innovation: China's RISC-V High-Performance Computing Initiative This speech examines RISC-V’s disruptive role in high-performance computing (HPC), highlighting global momentum and China’s accelerated progress through strategic policy support. One of this evolution is RiVAI Technologies’ Lingyu Processor—featuring a dual-core architecture, self-developed Core & NoC IP, and enterprise-grade RAS for data-center reliability. The speech further demonstrates a full-stack RISC-V HPC solution encompassing hardware co-developed with top OEMs and domestic software partners. Empowered by a robust ecosystem, RISC-V is advancing scenario-specific deployments (AI inference, industrial HPC) toward a multi-billion-dollar market, redefining next-generation computing infrastructure. Driving Open-Source Innovation: China's RISC-V High-Performance Computing Initiative This speech examines RISC-V’s disruptive role in high-performance computing (HPC), highlighting global momentum and China’s accelerated progress through strategic policy support. One of this evolution is RiVAI Technologies’ Lingyu Processor—featuring a dual-core architecture, self-developed Core & NoC IP, and enterprise-grade RAS for data-center reliability. The speech further demonstrates a full-stack RISC-V HPC solution encompassing hardware co-developed with top OEMs and domestic software partners. Empowered by a robust ecosystem, RISC-V is advancing scenario-specific deployments (AI inference, industrial HPC) toward a multi-billion-dollar market, redefining next-generation computing infrastructure.
Qingyuan Ren
Business VP, RiVAI Technologies
11:30 - 11:45 RISC-V Server Features of SpacemiT SoCs RISC-V Server Features of SpacemiT SoCs These foils focus on introducing total solution of RISC-V server implemented in SpacemiT RISC-V SoCs. SpacemiT SoC will present RISC-V server features including NUMA partial goods, RAS, HPM, BMC, virtualization, manageability, security, and etc. The discussion covers not only hardware implementation but also software solutions. RISC-V Server Features of SpacemiT SoCs RISC-V Server Features of SpacemiT SoCs These foils focus on introducing total solution of RISC-V server implemented in SpacemiT RISC-V SoCs. SpacemiT SoC will present RISC-V server features including NUMA partial goods, RAS, HPM, BMC, virtualization, manageability, security, and etc. The discussion covers not only hardware implementation but also software solutions.
Lv Zheng
Chief RISC-V Server Architect, SpacemiT
11:45 - 12:00 RISC-V + DSA: The Architectural Imperative Reshaping Compute Paradigms In the era of artificial intelligence, there is a need for an efficient, workload-optimized, and energy-efficient data center infrastructure. The emergence of Deepseek has made us realize that "the era of brute-forcing computing resource is over." By leveraging the open and flexibly scalable architecture of RISC-V to build domain-specific acceleration (DSA) solutions will be a new approach to reshaping the computing landscape.
LeapFive is promoting an international alliance. This alliance will integrate RISC-V computing chiplets. By optimizing the chiplet-to-chiplet interconnection standards, different DSA chiplets can interact to form the chips required for domain-specific applications. With the current shortage of RISC-V chips suitable for data center applications in the industry, it is hoped that this opportunity can share some of our practices and thoughts, so as to inspire our industry colleagues and jointly discuss the future development of "RISC-V + DSA". 		RISC-V + DSA: The Architectural Imperative Reshaping Compute Paradigms In the era of artificial intelligence, there is a need for an efficient, workload-optimized, and energy-efficient data center infrastructure. The emergence of Deepseek has made us realize that "the era of brute-forcing computing resource is over." By leveraging the open and flexibly scalable architecture of RISC-V to build domain-specific acceleration (DSA) solutions will be a new approach to reshaping the computing landscape.
LeapFive is promoting an international alliance. This alliance will integrate RISC-V computing chiplets. By optimizing the chiplet-to-chiplet interconnection standards, different DSA chiplets can interact to form the chips required for domain-specific applications. With the current shortage of RISC-V chips suitable for data center applications in the industry, it is hoped that this opportunity can share some of our practices and thoughts, so as to inspire our industry colleagues and jointly discuss the future development of "RISC-V + DSA".
Aglaia Kong
Founder & CEO, LeapFive
12:00 - 13:30 Lunch
Lunch
13:30 - 13:45 Innovative High-Performance Processor Implementation under RISC-V Architecture Innovative High-Performance Processor Implementation under RISC-V Architecture As innovations in LLM like DeepSeek pose unprecedented challenges to computational infrastructure, developing high-performance processors through foundational computing architecture innovations has become critical for the RISC-V ecosystem. This presentation will delve into cutting-edge architectural advancements of RISC-V in high-performance computing scenarios, and demonstrate how to develop world-leading RISC-V CPU products via groundbreaking computing architecture innovations. Innovative High-Performance Processor Implementation under RISC-V Architecture Innovative High-Performance Processor Implementation under RISC-V Architecture As innovations in LLM like DeepSeek pose unprecedented challenges to computational infrastructure, developing high-performance processors through foundational computing architecture innovations has become critical for the RISC-V ecosystem. This presentation will delve into cutting-edge architectural advancements of RISC-V in high-performance computing scenarios, and demonstrate how to develop world-leading RISC-V CPU products via groundbreaking computing architecture innovations.
Chang Liu
Director of CPU Design, Zhihe Computing
13:45 - 14:00 Progress and Prospects of RISC-V Software Ecosystem in HPC/Server Field In recent years, RISC-V has made significant progress in the field of high-performance computing/server. Many research institutions and enterprises have been actively engaged in the research and application development of RISC-V. From the hardware perspective, processors based on the RISC-V architecture have continuously improved their performance, gradually being able to meet the computing capacity requirements of high-performance computing and servers. Some advanced designs have achieved excellent performance in handling complex computing tasks through optimizing the core architecture, adding cache mechanisms, and adopting efficient interconnection technologies. Progress and Prospects of RISC-V Software Ecosystem in HPC/Server Field In recent years, RISC-V has made significant progress in the field of high-performance computing/server. Many research institutions and enterprises have been actively engaged in the research and application development of RISC-V. From the hardware perspective, processors based on the RISC-V architecture have continuously improved their performance, gradually being able to meet the computing capacity requirements of high-performance computing and servers. Some advanced designs have achieved excellent performance in handling complex computing tasks through optimizing the core architecture, adding cache mechanisms, and adopting efficient interconnection technologies.
Devin Xu
Senior Director of Software and Eco, Lanxin Computing
14:00 - 14:15 Application Practice of YiHua's Self-Developed RISC-V Core on DPU Application Practice of YiHua's Self-Developed RISC-V Core on DPU With data-intensive tasks and intelligent networks evolving rapidly, DPU has become the core of modern data centers and edge platforms. Our self-developed RISC-V Core & SoC for DPU leads in computing density, memory efficiency, and software compatibility, matching ARM N2/SiFive P550 in performance.
Featuring out-of-order execution, multi-level cache, and wide pipelines, the core excels in DPU workloads (packet forwarding, encryption, GEMM) at >2GHz, with SPECint/CoreMark comparable to commercial CPUs.
For high-performance scenarios, it natively supports RVV 1.0/IME/AME, enhancing batch access/sparse matrix tasks via memory optimizations. Key accelerations include Masked Memory Access (reducing redundancy), Strided Access (for structured data), and Matrix Tile Instructions (optimizing locality).
The DPDK/SPDK zero-copy framework directs DMA to user space with RVV libraries, cutting I/O latency/CPU usage. Validated in smart NICs/edge modules and supporting Linux, it offers scalability. We seek partners to co-build RISC-V platforms and discuss architecture/ecosystem/industry practices at the conference. 		Application Practice of YiHua's Self-Developed RISC-V Core on DPU Application Practice of YiHua's Self-Developed RISC-V Core on DPU With data-intensive tasks and intelligent networks evolving rapidly, DPU has become the core of modern data centers and edge platforms. Our self-developed RISC-V Core & SoC for DPU leads in computing density, memory efficiency, and software compatibility, matching ARM N2/SiFive P550 in performance.
Featuring out-of-order execution, multi-level cache, and wide pipelines, the core excels in DPU workloads (packet forwarding, encryption, GEMM) at >2GHz, with SPECint/CoreMark comparable to commercial CPUs.
For high-performance scenarios, it natively supports RVV 1.0/IME/AME, enhancing batch access/sparse matrix tasks via memory optimizations. Key accelerations include Masked Memory Access (reducing redundancy), Strided Access (for structured data), and Matrix Tile Instructions (optimizing locality).
The DPDK/SPDK zero-copy framework directs DMA to user space with RVV libraries, cutting I/O latency/CPU usage. Validated in smart NICs/edge modules and supporting Linux, it offers scalability. We seek partners to co-build RISC-V platforms and discuss architecture/ecosystem/industry practices at the conference.
Zhaoming Hu
Vice President, EHTech
14:15 - 14:30 RISC-V in the AI Era: Exploring Industry Adoption in Data Centers In the AI+ era, with computing power demands growing exponentially, data centers are facing multifaceted challenges in efficiency, cost, and supply chain autonomy. As an open instruction set architecture, RISC-V offers a transformative approach for data centers with its modularity, customizability, and energy-efficient advantages.
This discussion will focus on the industrial adoption of RISC-V in data centers, covering:
High-performance computing, storage optimization, and AI acceleration – analyzing technological breakthroughs and ecosystem challenges;
Real-world implementations across cloud, edge, and endpoint deployments;
The potential of RISC-V to reshape the future computing landscape. 		RISC-V in the AI Era: Exploring Industry Adoption in Data Centers In the AI+ era, with computing power demands growing exponentially, data centers are facing multifaceted challenges in efficiency, cost, and supply chain autonomy. As an open instruction set architecture, RISC-V offers a transformative approach for data centers with its modularity, customizability, and energy-efficient advantages.
This discussion will focus on the industrial adoption of RISC-V in data centers, covering:
High-performance computing, storage optimization, and AI acceleration – analyzing technological breakthroughs and ecosystem challenges;
Real-world implementations across cloud, edge, and endpoint deployments;
The potential of RISC-V to reshape the future computing landscape.
Yanan Liu
Director of Chip Technology, Mobile Cloud
14:30 - 14:45 Evaluation and Prospects of RISC-V Base Instruction Set in Data Center Context Evaluation and Prospects of RISC-V Base Instruction Set in Data Center Context The RISC-V instruction set was initially designed for low-power embedded applications. However, with the recent success of RISC-V processors in diverse application domains, RISC-V is gradually expanding into high-performance scenarios such as data centers. High-performance computing imposes distinct requirements on instruction set architectures compared to low-power applications. To evaluate the strengths and limitations of RISC-V in such scenarios, we conducted a multi-faceted assessment of the current RISC-V base instruction set through an in-depth analysis of program patterns derived from general-purpose performance benchmarks. Based on the findings, we propose a series of extensions and optimizations, some of which have already been ratified by the RISC-V community. Moving forward, we aim to collaborate with RISC-V vendors to advance the refinement and maturity of RISC-V for high-performance applications, including data centers. Evaluation and Prospects of RISC-V Base Instruction Set in Data Center Context Evaluation and Prospects of RISC-V Base Instruction Set in Data Center Context The RISC-V instruction set was initially designed for low-power embedded applications. However, with the recent success of RISC-V processors in diverse application domains, RISC-V is gradually expanding into high-performance scenarios such as data centers. High-performance computing imposes distinct requirements on instruction set architectures compared to low-power applications. To evaluate the strengths and limitations of RISC-V in such scenarios, we conducted a multi-faceted assessment of the current RISC-V base instruction set through an in-depth analysis of program patterns derived from general-purpose performance benchmarks. Based on the findings, we propose a series of extensions and optimizations, some of which have already been ratified by the RISC-V community. Moving forward, we aim to collaborate with RISC-V vendors to advance the refinement and maturity of RISC-V for high-performance applications, including data centers.
Junjie Hou
R&D Engineer, ByteDance
14:45 - 15:00 Intelligent Compression Applications and Optimizations Targeting RISC-V Video Transcoder Cards The rapid development of video surveillance services has led to an explosive growth in video data volume, bringing challenges such as high storage costs, high transmission bandwidth and heterogeneous encoding. Focusing on the rigid needs of vertical fields, China Telecom Research Institute has launched the industry's first RISC-V-based video transcoding card TeleVPU. The card is self-developed based on domestic RISC-V chips and has the dual capabilities of "transcoding + AI". It can greatly reduce the size of videos and has been efficiently verified in multiple rounds of tests and actual applications. With the deepening of applications, we have further carried out research on RISC-V intelligent compression: building a comprehensive and high-quality large-scale video data set covering diverse monitoring scenarios; designing an intelligent compression solution based on AI size models to assist VPU in achieving adaptive compression; completing the development of RISC-V intelligent compression tuning toolset to achieve high customizability and configurability, and is committed to meeting users' diverse compression needs. Intelligent Compression Applications and Optimizations Targeting RISC-V Video Transcoder Cards The rapid development of video surveillance services has led to an explosive growth in video data volume, bringing challenges such as high storage costs, high transmission bandwidth and heterogeneous encoding. Focusing on the rigid needs of vertical fields, China Telecom Research Institute has launched the industry's first RISC-V-based video transcoding card TeleVPU. The card is self-developed based on domestic RISC-V chips and has the dual capabilities of "transcoding + AI". It can greatly reduce the size of videos and has been efficiently verified in multiple rounds of tests and actual applications. With the deepening of applications, we have further carried out research on RISC-V intelligent compression: building a comprehensive and high-quality large-scale video data set covering diverse monitoring scenarios; designing an intelligent compression solution based on AI size models to assist VPU in achieving adaptive compression; completing the development of RISC-V intelligent compression tuning toolset to achieve high customizability and configurability, and is committed to meeting users' diverse compression needs.
Qian Wei
Researcher, China Telecommunication Research Institute
15:00 - 15:30 Tea Break
Tea Break
15:30 - 15:45 RISC-V CoVE Implementation In Privileged Firmware In the confidential computing CoVE solution, RISC-V provides a classic type of privileged firmware running in machine privilege mode, as referred to RDSM (RoT domain Security Manager). This presentation primarily introduces those new extensive components to meet critical security requirements defined in RISC-V Server SoC specification version v1.0. All new components introduced to RDSM comply with NIST SP 800-193 and ISO/IEC 20831 standards, and ensure compliance with global confidential computing requirements. RISC-V CoVE Implementation In Privileged Firmware In the confidential computing CoVE solution, RISC-V provides a classic type of privileged firmware running in machine privilege mode, as referred to RDSM (RoT domain Security Manager). This presentation primarily introduces those new extensive components to meet critical security requirements defined in RISC-V Server SoC specification version v1.0. All new components introduced to RDSM comply with NIST SP 800-193 and ISO/IEC 20831 standards, and ensure compliance with global confidential computing requirements.
Xiaoxia Cui
Senior Security Expert, Alibaba DAMO Academy
15:45 - 16:00 Exploration and Practice of RISC-V Applications in Carrier Services China Mobile is driving breakthroughs in RISC-V for high-performance data centers through cross-industry collaboration, tackling full-stack technological challenges and building expertise from instruction set optimization to 5G server design. At the instruction set level, targeting 5G requirements, we expanded the RISC-V architecture through scalar, vector, and matrix instruction enhancements, significantly boosting performance and energy efficiency. In server development, CMCC analyzed 5G core network requirements, defined critical metrics, and co-developed industry-first fully RISC-V based servers with partners. To accelerate industry adoption, we are building 5G+RISC-V demonstration zones to establish benchmarks, exploring 6G-AI-native convergence frameworks, finalizing RISC-V AI instruction set standards, etc. These efforts not only provide computing power support for operator network transformation but also drive the coordinated development of China's RISC-V industrial chain—spanning IP core development, chip manufacturing, system integration, and server production—through demand traction, thereby accelerating the construction of an open and win-win RISC-V industry ecosystem. Exploration and Practice of RISC-V Applications in Carrier Services China Mobile is driving breakthroughs in RISC-V for high-performance data centers through cross-industry collaboration, tackling full-stack technological challenges and building expertise from instruction set optimization to 5G server design. At the instruction set level, targeting 5G requirements, we expanded the RISC-V architecture through scalar, vector, and matrix instruction enhancements, significantly boosting performance and energy efficiency. In server development, CMCC analyzed 5G core network requirements, defined critical metrics, and co-developed industry-first fully RISC-V based servers with partners. To accelerate industry adoption, we are building 5G+RISC-V demonstration zones to establish benchmarks, exploring 6G-AI-native convergence frameworks, finalizing RISC-V AI instruction set standards, etc. These efforts not only provide computing power support for operator network transformation but also drive the coordinated development of China's RISC-V industrial chain—spanning IP core development, chip manufacturing, system integration, and server production—through demand traction, thereby accelerating the construction of an open and win-win RISC-V industry ecosystem.
Xiaowei Wu
Project Manager, China Mobile Research Institute
16:00 - 16:15 Ventus GPGPU: Latest Advancements in a High-Performance Full-Stack Open-Source GPGPU Based on RISC-V This session introduces Ventus, a leading open-source, full-stack General-Purpose GPU (GPGPU) designed for the RISC-V ecosystem. We will present the latest significant advancements that are transitioning the project from a promising academic concept to a mature, feature-rich platform ready for complex workloads.
Attendees will get a comprehensive overview of key updates across the entire stack. This includes major ISA enhancements that support generic memory addressing and 64-bit computation, new RTL developments like a multi-precision Tensor Core, and our sophisticated verification framework featuring the GPU Verification Model (GVM).
Furthermore, we will share the latest results and experiences from our hardware prototyping on FPGAs, and discuss our ongoing work towards a high-bandwidth, PCIe-based validation platform. This talk offers deep insights into the architecture and implementation of a cutting-edge, open-source GPU, showcasing a practical path forward for accelerating HPC and AI applications on RISC-V. 		Ventus GPGPU: Latest Advancements in a High-Performance Full-Stack Open-Source GPGPU Based on RISC-V This session introduces Ventus, a leading open-source, full-stack General-Purpose GPU (GPGPU) designed for the RISC-V ecosystem. We will present the latest significant advancements that are transitioning the project from a promising academic concept to a mature, feature-rich platform ready for complex workloads.
Attendees will get a comprehensive overview of key updates across the entire stack. This includes major ISA enhancements that support generic memory addressing and 64-bit computation, new RTL developments like a multi-precision Tensor Core, and our sophisticated verification framework featuring the GPU Verification Model (GVM).
Furthermore, we will share the latest results and experiences from our hardware prototyping on FPGAs, and discuss our ongoing work towards a high-bandwidth, PCIe-based validation platform. This talk offers deep insights into the architecture and implementation of a cutting-edge, open-source GPU, showcasing a practical path forward for accelerating HPC and AI applications on RISC-V.
Mingyuan Ma
PhD Student, School of Integrated Circuits, Tsinghua University
16:15 - 16:30 RISC-V Heterogenous Programming Paradigm: Atomic I/O Enqueue and IOMMU GIPC extensions In the era of artificial intelligence, general-purpose processors can no longer meet the demands of diverse computing workloads, and heterogeneous computing has emerged as the mainstream approach. For instance, high-dimensional tensor computing workloads can be offloaded to TPUs, while data stream workloads can be offloaded to DPUs. So, the challenge of efficiently managing DSAs in heterogeneous systems has become a prominent industry focus, driving ISA advancements:
- Armv8.7/9.2 has incorporated ST64BV0 instructions
- The x86 architecture has implemented ENQCMD instructions These ISA innovations collectively reduce control latency and optimize system resource utilization.
To help RISC-V adapt to this trend, the presentation introduces two proposals: 1) Atomic IO Enqueue Extension (AIOE for ISA), 2) AIOE virtualization (GIPC for IOMMU).
The AIOE is an ISA spec extension, which involves new instructions, PMA, and CSRs. AIOE virtualization involves a new extension for RISC-V IOMMU (a non-ISA spec) called G-stage table In Process Context (GIPC). With the help of AIOE and GIPC, RISC-V can explore a new heterogeneous programming paradigm from HPC to embedded scenarios. 		RISC-V Heterogenous Programming Paradigm: Atomic I/O Enqueue and IOMMU GIPC extensions In the era of artificial intelligence, general-purpose processors can no longer meet the demands of diverse computing workloads, and heterogeneous computing has emerged as the mainstream approach. For instance, high-dimensional tensor computing workloads can be offloaded to TPUs, while data stream workloads can be offloaded to DPUs. So, the challenge of efficiently managing DSAs in heterogeneous systems has become a prominent industry focus, driving ISA advancements:
- Armv8.7/9.2 has incorporated ST64BV0 instructions
- The x86 architecture has implemented ENQCMD instructions These ISA innovations collectively reduce control latency and optimize system resource utilization.
To help RISC-V adapt to this trend, the presentation introduces two proposals: 1) Atomic IO Enqueue Extension (AIOE for ISA), 2) AIOE virtualization (GIPC for IOMMU).
The AIOE is an ISA spec extension, which involves new instructions, PMA, and CSRs. AIOE virtualization involves a new extension for RISC-V IOMMU (a non-ISA spec) called G-stage table In Process Context (GIPC). With the help of AIOE and GIPC, RISC-V can explore a new heterogeneous programming paradigm from HPC to embedded scenarios.
Ren Guo
Staff Engineer, Alibaba DAMO Academy
16:30 - 16:45 RISC-V Instruction Extensions for Radio Signal Modulation Recognition To address the high computational power and real-time requirements for radio signal modulation recognition tasks, this paper designs a domain-specific processor based on the extensible instruction set architecture of RISC-V. By optimizing the processor architecture and extending custom instructions, coupled with improvements to the modulation recognition algorithm, we achieve hardware-software co-acceleration for modulation recognition tasks. The complete processor code is prototyped and validated on an FPGA (Field-Programmable Gate Array). Test results demonstrate that the algorithm achieves over 95% accuracy in recognizing modulation types under SNR (Signal to Noise Ratio) >14 dB, with 100% accuracy for 2PSK (2 Phase Shift Keying) and 4PSK (4 Phase Shift Keying). The execution cycles for the FFT (Fast Fourier Transform)—a critical part of the recognition algorithm—are reduced from 102,070 to 2,266 after optimization. RISC-V Instruction Extensions for Radio Signal Modulation Recognition To address the high computational power and real-time requirements for radio signal modulation recognition tasks, this paper designs a domain-specific processor based on the extensible instruction set architecture of RISC-V. By optimizing the processor architecture and extending custom instructions, coupled with improvements to the modulation recognition algorithm, we achieve hardware-software co-acceleration for modulation recognition tasks. The complete processor code is prototyped and validated on an FPGA (Field-Programmable Gate Array). Test results demonstrate that the algorithm achieves over 95% accuracy in recognizing modulation types under SNR (Signal to Noise Ratio) >14 dB, with 100% accuracy for 2PSK (2 Phase Shift Keying) and 4PSK (4 Phase Shift Keying). The execution cycles for the FFT (Fast Fourier Transform)—a critical part of the recognition algorithm—are reduced from 102,070 to 2,266 after optimization.
Meng Li
Faculty of School of Microelectronics of School of Electronic and Information Engineering, Xi'an Jiaotong University
16:45 - 17:00 Fine-Grained Calibration of RISC-V Simulators via Cliff Benchmarks The rapid evolution of RISC-V processors and the growing momentum of open-source hardware have significantly increased the complexity of CPU design. Architectural simulators offer an efficient means to explore and accelerate the development of open-source CPUs. However, inaccuracies in modeling can substantially undermine their effectiveness. Traditional calibration techniques often fail to pinpoint the root causes of performance discrepancies, as they operate at coarse granularity and struggle to disentangle the effects of individual microarchitectural features.
To address this, we propose Microarchitecture Cliffs (Cliff) — a benchmark generation methodology that constructs minimal and highly targeted benchmarks to isolate the impact of individual architectural components. The core idea behind Cliff is to construct minimal, targeted benchmarks that exert controlled and progressively increasing pressure on specific microarchitectural components, enabling clear and quantifiable attribution of performance variation to individual features. This approach provides a direct and actionable mapping between simulator behavior and architectural characteristics observed in RTL. 		Fine-Grained Calibration of RISC-V Simulators via Cliff Benchmarks The rapid evolution of RISC-V processors and the growing momentum of open-source hardware have significantly increased the complexity of CPU design. Architectural simulators offer an efficient means to explore and accelerate the development of open-source CPUs. However, inaccuracies in modeling can substantially undermine their effectiveness. Traditional calibration techniques often fail to pinpoint the root causes of performance discrepancies, as they operate at coarse granularity and struggle to disentangle the effects of individual microarchitectural features.
To address this, we propose Microarchitecture Cliffs (Cliff) — a benchmark generation methodology that constructs minimal and highly targeted benchmarks to isolate the impact of individual architectural components. The core idea behind Cliff is to construct minimal, targeted benchmarks that exert controlled and progressively increasing pressure on specific microarchitectural components, enabling clear and quantifiable attribution of performance variation to individual features. This approach provides a direct and actionable mapping between simulator behavior and architectural characteristics observed in RTL.
Hao Zhen
Engineer, Institute of Computing Technology, Chinese Academy of Sciences
Engineer, Beijing Institute of Open Source Chip
Qingxuan Kang
PhD Candidate at National University of Singapore
17:00 - 17:15 Enabling Next-Generation Computing Architecture with RISC-V and Virtual Instruction Technology Enabling Next-Generation Computing Architecture with RISC-V and Virtual Instruction Technology
Enabling Next-Generation Computing Architecture with RISC-V and Virtual Instruction Technology Enabling Next-Generation Computing Architecture with RISC-V and Virtual Instruction Technology
Yi Yang
COO, EVAS Intelligence
Software & Ecosystem
Host:
Yanjun Wu, Deputy Director & Chief Engineer, Institute of Software, Chinese Academy of SciencesJiangang Duan, R&D Director, Intel China; Senior Advisor, Shanghai Open Processor Industry Innovation Center (SOPIC)
7/18 9:00-17:30
Room 304
Time Title SpeakerTitle & Speaker
09:00 - 09:15 openEuler for RISC-V Servers: Challenges & Roadmap openEuler for RISC-V Servers: Challenges & Roadmap With the release of the RISC-V Server Platform SPEC and with strong backing from RISC-V International, RISE, and other leading vendors standardized RISC-V servers, featuring cutting edge IP, are set to debut around 2025 and 2026. As a dedicated server operating system, openEuler is ideally positioned to capitalize on this momentum. In our upcoming 26.03 release, openEuler will offer comprehensive support for the RISC-V Server Platform SPEC. Our clearly defined roadmap takes a phased approach to addressing both kernel and userspace requirements beginning with robust kernel support by enabling the 6.6 LTS kernel to integrate ServerPlatform Generic Drivers and validating the RVA23 standard, followed by targeted userspace enhancements. In this initial phase, our optimization efforts will focus on enhancing performance for compile and storage servers, while we actively collaborate with hardware vendors to establish a robust, unified kernel foundation. openEuler for RISC-V Servers: Challenges & Roadmap openEuler for RISC-V Servers: Challenges & Roadmap With the release of the RISC-V Server Platform SPEC and with strong backing from RISC-V International, RISE, and other leading vendors standardized RISC-V servers, featuring cutting edge IP, are set to debut around 2025 and 2026. As a dedicated server operating system, openEuler is ideally positioned to capitalize on this momentum. In our upcoming 26.03 release, openEuler will offer comprehensive support for the RISC-V Server Platform SPEC. Our clearly defined roadmap takes a phased approach to addressing both kernel and userspace requirements beginning with robust kernel support by enabling the 6.6 LTS kernel to integrate ServerPlatform Generic Drivers and validating the RVA23 standard, followed by targeted userspace enhancements. In this initial phase, our optimization efforts will focus on enhancing performance for compile and storage servers, while we actively collaborate with hardware vendors to establish a robust, unified kernel foundation.
Sheng Qu
Senior Engineer, Institute of Software, Chinese Academy of Sciences
09:15 - 09:30 RedHat's Latest Progress and Trends in the RISC-V Software and Hardware Ecosystem RedHat's Latest Progress and Trends in the RISC-V Software and Hardware Ecosystem This talk provides a detailed overview of the rapid growth of RISC-V across both hardware and software. Then focuses on how Red Hat has been enabling RISC-V on its three distributions: Fedora, CentOS Stream, and Red Hat Enterprise Linux (RHEL).
Using Fedora as example, we go through the historical development and current status of these distributions on RISC-V, highlighting key milestones, technical challenges, and ongoing efforts. The session concludes with an outlook on the broader RISC-V ecosystem and its readiness to support the next wave of innovation in the AI era. 		RedHat's Latest Progress and Trends in the RISC-V Software and Hardware Ecosystem RedHat's Latest Progress and Trends in the RISC-V Software and Hardware Ecosystem This talk provides a detailed overview of the rapid growth of RISC-V across both hardware and software. Then focuses on how Red Hat has been enabling RISC-V on its three distributions: Fedora, CentOS Stream, and Red Hat Enterprise Linux (RHEL).
Using Fedora as example, we go through the historical development and current status of these distributions on RISC-V, highlighting key milestones, technical challenges, and ongoing efforts. The session concludes with an outlook on the broader RISC-V ecosystem and its readiness to support the next wave of innovation in the AI era.
Wei Fu
Principal Software Engineer, Red Hat
09:30 - 09:45 Recent Advances and Future Roadmap of openKylin on the RISC-V Architecture Recent Advances and Future Roadmap of openKylin on the RISC-V Architecture This presentation introduces the latest technical progress and development roadmap of openKylin on the RISC-V architecture. Key efforts include unifying openKylin kernel versions across major hardware vendors such as C-SKY, Eswin, and T-Head to ensure baseline compatibility and consistency across the RISC-V platform. Through software-hardware collaboration, openKylin has optimized scheduling mechanisms and system performance, enhancing overall efficiency. In ecosystem development, the focus is on adapting mainstream applications and frameworks to RISC-V. A dedicated software repository built around the RVA23 architecture provides a unified and stable foundation for application deployment, accelerating software adaptation and iteration.
Looking ahead, the openKylin community will further explore the potential of the RISC-V platform by strengthening collaboration with chip vendors, academia, and developer communities. Efforts will continue to deepen the integration of RISC-V and open-source operating systems, support industrial deployment, and help build an open, robust, and prosperous RISC-V software ecosystem. 		Recent Advances and Future Roadmap of openKylin on the RISC-V Architecture Recent Advances and Future Roadmap of openKylin on the RISC-V Architecture This presentation introduces the latest technical progress and development roadmap of openKylin on the RISC-V architecture. Key efforts include unifying openKylin kernel versions across major hardware vendors such as C-SKY, Eswin, and T-Head to ensure baseline compatibility and consistency across the RISC-V platform. Through software-hardware collaboration, openKylin has optimized scheduling mechanisms and system performance, enhancing overall efficiency. In ecosystem development, the focus is on adapting mainstream applications and frameworks to RISC-V. A dedicated software repository built around the RVA23 architecture provides a unified and stable foundation for application deployment, accelerating software adaptation and iteration.
Looking ahead, the openKylin community will further explore the potential of the RISC-V platform by strengthening collaboration with chip vendors, academia, and developer communities. Efforts will continue to deepen the integration of RISC-V and open-source operating systems, support industrial deployment, and help build an open, robust, and prosperous RISC-V software ecosystem.
Zhuoheng Li
RISC-V SIG Maintainer, openKylin
09:45 - 10:00 The Evolution of the RISC-V Toolchain: A Year in Review and the Road Ahead The Evolution of the RISC-V Toolchain: A Year in Review and the Road Ahead This talk presents a comprehensive review of the RISC-V toolchain advancements over the past year, focusing on key updates in both GCC and LLVM. In GCC 15, major improvements include enhanced auto-vectorization, improved vector code generation, broader ISA extension support, function multiversioning, and initial support for control-flow integrity (CFI). Similarly, LLVM 20 continues to expand extension coverage and introduces CFI support as well.
In addition to reviewing completed work, this session will highlight ongoing development efforts and future plans, with a particular focus on upcoming N32 ABI support and the current status of psABI evolution. Attendees will gain a clear understanding of the recent progress and future direction in RISC-V toolchain development across instruction set support, performance, security, and ABI standardization. 		The Evolution of the RISC-V Toolchain: A Year in Review and the Road Ahead The Evolution of the RISC-V Toolchain: A Year in Review and the Road Ahead This talk presents a comprehensive review of the RISC-V toolchain advancements over the past year, focusing on key updates in both GCC and LLVM. In GCC 15, major improvements include enhanced auto-vectorization, improved vector code generation, broader ISA extension support, function multiversioning, and initial support for control-flow integrity (CFI). Similarly, LLVM 20 continues to expand extension coverage and introduces CFI support as well.
In addition to reviewing completed work, this session will highlight ongoing development efforts and future plans, with a particular focus on upcoming N32 ABI support and the current status of psABI evolution. Attendees will gain a clear understanding of the recent progress and future direction in RISC-V toolchain development across instruction set support, performance, security, and ABI standardization.
Kito Cheng
RISC-V Toolchain Developer, SiFive
10:00 - 10:15 Latest Progress of QEMU Community in RISC-V Ecosystem (2024-2025) Latest Progress of QEMU Community in RISC-V Ecosystem (2024-2025) Over the past year, the QEMU community has achieved significant advancements in RISC-V architecture support, enhancing its capabilities for both developers and enterprise applications. Key highlights include:
1）RVA23 Profile Compliance.
2）Efficient Improvements on RISC-V Vector Extension (RVV) emulation.
3) Security Enhancements Extensions, including Control-Flow Integrity (CFI) and Pointer Masking.
4) Virtualization & I/O Innovations, IOMMU Support and SMMPT.
5) OCP Format Support, including fp8, fp6, fp4 format for AI.
6) Server SoC and UEFI.
7) Deterministic Multi-Core Execution.
8) KVM Accelerator. 		Latest Progress of QEMU Community in RISC-V Ecosystem (2024-2025) Latest Progress of QEMU Community in RISC-V Ecosystem (2024-2025) Over the past year, the QEMU community has achieved significant advancements in RISC-V architecture support, enhancing its capabilities for both developers and enterprise applications. Key highlights include:
1）RVA23 Profile Compliance.
2）Efficient Improvements on RISC-V Vector Extension (RVV) emulation.
3) Security Enhancements Extensions, including Control-Flow Integrity (CFI) and Pointer Masking.
4) Virtualization & I/O Innovations, IOMMU Support and SMMPT.
5) OCP Format Support, including fp8, fp6, fp4 format for AI.
6) Server SoC and UEFI.
7) Deterministic Multi-Core Execution.
8) KVM Accelerator.
Zhiwei Liu
Software Engineer, RISC-V & Ecosystem Department, Alibaba DAMO Academy
10:15 - 10:45 Tea Break
Tea Break
10:45 - 11:00 x264 RISC-V Ecosystem Building and Optimization x264 RISC-V Ecosystem Building and Optimization Video transcoding is one of the important workloads in ByteDance's data center. The RISC-V ecosystem of FFmpeg has made significant progress. In particular, a large number of RVV implementations have been completed for decoders such as Dav1d and h264. However, there has been relatively little progress in encoders. This topic will introduce the RISC-V development progress of the x264 encoder by ByteDance's software ecosystem team, the GAP in the RVV instruction set discovered from it, and the instruction extension design proposed in the community. Finally, it will discuss the problems and challenges faced by the RISC-V software ecosystem. x264 RISC-V Ecosystem Building and Optimization x264 RISC-V Ecosystem Building and Optimization Video transcoding is one of the important workloads in ByteDance's data center. The RISC-V ecosystem of FFmpeg has made significant progress. In particular, a large number of RVV implementations have been completed for decoders such as Dav1d and h264. However, there has been relatively little progress in encoders. This topic will introduce the RISC-V development progress of the x264 encoder by ByteDance's software ecosystem team, the GAP in the RVV instruction set discovered from it, and the instruction extension design proposed in the community. Finally, it will discuss the problems and challenges faced by the RISC-V software ecosystem.
Jiayan Qian
Software Engineer, ByteDance
11:00 - 11:15 RISC-V in Data Center Software Ecosystem: Opportunities and Challenges RISC-V in Data Center Software Ecosystem: Opportunities and Challenges It is expected that high-performance CPUs that support the RVA23 instruction set will be commercially released from 2025 to 2026. To quickly promote industrial implementation, basic software needs to be planned and promoted in advance. Currently, the community version OS and basic libraries only support RVA20, so it is necessary to accelerate the construction of RVA23 related software RISC-V in Data Center Software Ecosystem: Opportunities and Challenges RISC-V in Data Center Software Ecosystem: Opportunities and Challenges It is expected that high-performance CPUs that support the RVA23 instruction set will be commercially released from 2025 to 2026. To quickly promote industrial implementation, basic software needs to be planned and promoted in advance. Currently, the community version OS and basic libraries only support RVA20, so it is necessary to accelerate the construction of RVA23 related software
Yunxiang Jia
RISC-V Ecosystem Leader, Software Architecture Design and Performance Expert, ZTE
11:15 - 11:30 Shape Graphic for RISC-V Shape Graphic for RISC-V Open source is a big drive to improve the whole society efficiency, RISC-V ISA is a good example, but there are still a lot of black boxes in RISC-V based designs, graphic is the most difficult one. In this session, I want to share the status and actions from Imagination Technologies to improve open source GPU software stack. Shape Graphic for RISC-V Shape Graphic for RISC-V Open source is a big drive to improve the whole society efficiency, RISC-V ISA is a good example, but there are still a lot of black boxes in RISC-V based designs, graphic is the most difficult one. In this session, I want to share the status and actions from Imagination Technologies to improve open source GPU software stack.
Zheng Zhang
Principal Solutions Architect, Imagination Technologies
11:30 - 11:45 The Road to RISC-V Server Standardization: UEFI Boot, Boot and Runtime Services The Road to RISC-V Server Standardization: UEFI Boot, Boot and Runtime Services During the Boot process of RISC-V high-performance servers, most ISAs and servers manufacturers use UEFI BIOS. However, On the RISC-V platform, there are still many UEFI BIOS are customized. The absence and ambiguity of the UEFI (ACPI/SmBIOS) spec on RISC-V is an important reason.
In order to standardize UEFI on RISC-V and improve the hardware compatibility of UEFI on RISC-V, the SHANDONG University team built the Dongshan No.1 RISC-V server cluster (SG2042), and combined with other RISC-V64 platforms and Qemu simulation, A series of explorations were carried out on UEFI + RISC-V server boot. The main work was to build the framework of RISC-V server UEFI BIOS, and contribute the EDK2/ EDk2-Platform code related to RISC-V ACPI /SmBios in the UEFI community. To promote the release and implementation of RISC-V Boot & Runtime Services (BRS) is also one of their item . 		The Road to RISC-V Server Standardization: UEFI Boot, Boot and Runtime Services The Road to RISC-V Server Standardization: UEFI Boot, Boot and Runtime Services During the Boot process of RISC-V high-performance servers, most ISAs and servers manufacturers use UEFI BIOS. However, On the RISC-V platform, there are still many UEFI BIOS are customized. The absence and ambiguity of the UEFI (ACPI/SmBIOS) spec on RISC-V is an important reason.
In order to standardize UEFI on RISC-V and improve the hardware compatibility of UEFI on RISC-V, the SHANDONG University team built the Dongshan No.1 RISC-V server cluster (SG2042), and combined with other RISC-V64 platforms and Qemu simulation, A series of explorations were carried out on UEFI + RISC-V server boot. The main work was to build the framework of RISC-V server UEFI BIOS, and contribute the EDK2/ EDk2-Platform code related to RISC-V ACPI /SmBios in the UEFI community. To promote the release and implementation of RISC-V Boot & Runtime Services (BRS) is also one of their item .
Zhen Liu
Firmware Engineer, Software College, Shandong University
Evan Chai
Senior Technical Expert, Alibaba DAMO Academy
11:45 - 12:00 RVCK Project: Driving openEuler on RISC-V RVCK Project: Driving openEuler on RISC-V To bridge the gap between the rapid evolution of the RISC-V architecture, driven by the RVA23 specification, and the industry's demand for a stable Long-Term Support (LTS) kernel, the openEuler community has initiated the RVCK project. The project's mission is to deliver a unified and feature-rich LTS kernel based on Linux 6.6.
RVCK focuses on enabling critical server-grade functionality, including advanced interrupt architecture (AIA), IOMMU, enhanced KVM virtualization, and comprehensive platform support via ACPI and SBI. By collaborating with key hardware partners, this project accelerates product validation and streamlines upstream contributions.
Ultimately, RVCK establishes the essential technical cornerstone for the commercial adoption of RISC-V servers, driving the strategic goal of making openEuler a Tier 1 platform for this growing ecosystem. 		RVCK Project: Driving openEuler on RISC-V RVCK Project: Driving openEuler on RISC-V To bridge the gap between the rapid evolution of the RISC-V architecture, driven by the RVA23 specification, and the industry's demand for a stable Long-Term Support (LTS) kernel, the openEuler community has initiated the RVCK project. The project's mission is to deliver a unified and feature-rich LTS kernel based on Linux 6.6.
RVCK focuses on enabling critical server-grade functionality, including advanced interrupt architecture (AIA), IOMMU, enhanced KVM virtualization, and comprehensive platform support via ACPI and SBI. By collaborating with key hardware partners, this project accelerates product validation and streamlines upstream contributions.
Ultimately, RVCK establishes the essential technical cornerstone for the commercial adoption of RISC-V servers, driving the strategic goal of making openEuler a Tier 1 platform for this growing ecosystem.
Jingwei Wang
OS Engineer, Institute of Software, Chinese Academy of Sciences
openEuler TC Member
12:00 - 13:30 Lunch
Lunch
13:30 - 13:45 Porting OP-TEE on RISC-V: A Practical Guide and Introduction Porting OP-TEE on RISC-V: A Practical Guide and Introduction In this presentation, we will guide you through how to set up OP-TEE on a RISC-V platform, using a SiFive platform as our target. We’ll begin with an introduction to Trusted Execution Environment (TEE) architecture, discussing its importance in modern secure systems, especially in the embedded and IoT domains. Next, we’ll walk through the boot flow on the SMP system and explain key configuration.
This section also provides a comprehensive overview of RISC-V’s security features, focusing on those that enhance trusted execution environments. We will examine hardware-based protections and how they reinforce OP-TEE to deliver secure computing at runtime.
Additionally, we’ll share some OP-TEE debug configurations that help troubleshoot common setup errors.
At the end, we’ll discuss the current progress of OP-TEE on RISC-V platforms and ongoing upstream contributions. Finally, we’ll share our roadmap for OP-TEE and RISC-V development in 2025. 		Porting OP-TEE on RISC-V: A Practical Guide and Introduction Porting OP-TEE on RISC-V: A Practical Guide and Introduction In this presentation, we will guide you through how to set up OP-TEE on a RISC-V platform, using a SiFive platform as our target. We’ll begin with an introduction to Trusted Execution Environment (TEE) architecture, discussing its importance in modern secure systems, especially in the embedded and IoT domains. Next, we’ll walk through the boot flow on the SMP system and explain key configuration.
This section also provides a comprehensive overview of RISC-V’s security features, focusing on those that enhance trusted execution environments. We will examine hardware-based protections and how they reinforce OP-TEE to deliver secure computing at runtime.
Additionally, we’ll share some OP-TEE debug configurations that help troubleshoot common setup errors.
At the end, we’ll discuss the current progress of OP-TEE on RISC-V platforms and ongoing upstream contributions. Finally, we’ll share our roadmap for OP-TEE and RISC-V development in 2025.
Peter Lin
RISC-V System Software Developer, SiFive
13:45 - 14:00 Architecting TEEs with RV-ACRN Hypervisor on RISC-V Platforms Architecting TEEs with RV-ACRN Hypervisor on RISC-V Platforms Trusted execution environments (TEEs) are being used widely in IOT, edge and mobile devices, which require isolating the security-critical functionalities into separate execution environments and protecting them from the untrusted OS. RISC-V architecture applies this approach by providing hardware-based partitioning of the system with either PMP/IOPMP or H-Ext/IOMMU ISA extensions, which leads to the different SoC security architectures in real world of RISC-V system design. With RV-ACRN hypervisor technology, we have designed and implemented an unified end-to-end solution to run OP-TEE on the diverse RISC-V platforms to enable commercial TAs. The RV-ACRN hypervisor supports two working modes: m-ACRN running in M-mode with mem partitioning based on PMP/IOPMP and vCPU context switch in pure software way; h-ACRN running in HS-mode with full virtualization support accelerated by H-Ext/IOMMU. In this talk, I'll present how ACRN-based TEE solutions run on different RISC-V hardware configurations and demonstrate the strengths of our design in terms of security, flexibility, and practicability on RISC-V platforms. Architecting TEEs with RV-ACRN Hypervisor on RISC-V Platforms Architecting TEEs with RV-ACRN Hypervisor on RISC-V Platforms Trusted execution environments (TEEs) are being used widely in IOT, edge and mobile devices, which require isolating the security-critical functionalities into separate execution environments and protecting them from the untrusted OS. RISC-V architecture applies this approach by providing hardware-based partitioning of the system with either PMP/IOPMP or H-Ext/IOMMU ISA extensions, which leads to the different SoC security architectures in real world of RISC-V system design. With RV-ACRN hypervisor technology, we have designed and implemented an unified end-to-end solution to run OP-TEE on the diverse RISC-V platforms to enable commercial TAs. The RV-ACRN hypervisor supports two working modes: m-ACRN running in M-mode with mem partitioning based on PMP/IOPMP and vCPU context switch in pure software way; h-ACRN running in HS-mode with full virtualization support accelerated by H-Ext/IOMMU. In this talk, I'll present how ACRN-based TEE solutions run on different RISC-V hardware configurations and demonstrate the strengths of our design in terms of security, flexibility, and practicability on RISC-V platforms.
Haicheng Li
System Software Architect, Intel
14:00 - 14:15 Towards Secure Container Infrastructure on RISC-V: the Development from Rust-vmm to Kata-Containers As the computing industry moves toward more secure infrastructures, the need for secure container infrastructure on RISC-V like Kata-Containers is emerging.
We will introduce the current development status of a complete Rust virtualization software stack (rust-vmm -> cloud-hypervisor -> kata-containers) for future RISC-V SoCs compliant with the RVA23 specification and server platform standards, which effectively using "real" KVM (not "virtual" KVM as it is now). 		Towards Secure Container Infrastructure on RISC-V: the Development from Rust-vmm to Kata-Containers As the computing industry moves toward more secure infrastructures, the need for secure container infrastructure on RISC-V like Kata-Containers is emerging.
We will introduce the current development status of a complete Rust virtualization software stack (rust-vmm -> cloud-hypervisor -> kata-containers) for future RISC-V SoCs compliant with the RVA23 specification and server platform standards, which effectively using "real" KVM (not "virtual" KVM as it is now).
Ruoqing He
Software Engineer, Institute of Software, Chinese Academy of Sciences
14:15 - 14:30 A Standard-compliant High Performance RISC-V Desktop Virtualization Platform
A Standard-compliant High Performance RISC-V Desktop Virtualization Platform
Ken Xia
Software Director, UltraRISC
14:30 - 14:45 Enabling System Standby with RISC-V platform RISC-V, an open standard instruction set architecture (ISA), has gained significant attention across diverse applications due to its flexibility, extensibility, and open-source nature. Its modular design allows developers to create customized instruction sets that optimize power consumption and performance for specific tasks, such as edge computing devices, wearables and smart home devices. Despite its advantages, as of September 2023, the full establishment of a software ecosystem and the implementation of comprehensive power management functionality in RISC-V remain a work in progress. This study delves into the integration of power management within the RISC-V software ecosystem, culminating in a successful commercial product. The implementation achieves a power consumption metric of less than 10mW for the system-on-chip (SoC) and less than 5ms of wake-up latency. By September 2024, this functionality was successfully adapted for the Th1520-powered RuyiBook laptop. These advancements underscore the potential of RISC-V in improving energy efficiency in edge computing applications, paving the way for future innovations in power management and system optimization. Enabling System Standby with RISC-V platform RISC-V, an open standard instruction set architecture (ISA), has gained significant attention across diverse applications due to its flexibility, extensibility, and open-source nature. Its modular design allows developers to create customized instruction sets that optimize power consumption and performance for specific tasks, such as edge computing devices, wearables and smart home devices. Despite its advantages, as of September 2023, the full establishment of a software ecosystem and the implementation of comprehensive power management functionality in RISC-V remain a work in progress. This study delves into the integration of power management within the RISC-V software ecosystem, culminating in a successful commercial product. The implementation achieves a power consumption metric of less than 10mW for the system-on-chip (SoC) and less than 5ms of wake-up latency. By September 2024, this functionality was successfully adapted for the Th1520-powered RuyiBook laptop. These advancements underscore the potential of RISC-V in improving energy efficiency in edge computing applications, paving the way for future innovations in power management and system optimization.
Fengxue Zhang
Senior Engineer, Alibaba DAMO Academy
14:45 - 15:00 Exploration of Virtualization Technology Based on BeiHai Cloud Computing Experimental Platform Exploration of Virtualization Technology Based on BeiHai Cloud Computing Experimental Platform Currently, the performance and ecosystem of RISC-V chips are limited, and the industry lacks a large-scale cloud computing cluster verification environment, which restricts the application and promotion of RISC-V in the field of cloud computing. In response to this issue, China Telecom Research Institute has launched the BeiHai RISC-V cloud computing experimental platform, which has built a complete solution based on hardware facilities such as RISC-V servers, TPU, VPU, and Kubernetes based application platforms. At present, the BeiHai platform has added RISC-V virtualization capabilities. In this speech, we will first introduce the BeiHai platform and the newly added hardware virtualization capabilities. Then, we will introduce KubeVirt adaptation based on the BeiHai platform. In the speech, we will introduce the methods and difficulties of adapting each component of KubeVirt to the RISC-V architecture, as well as the application exploration of building virtual machine and container resource pools based on RISC-V hardware, promoting the application of RISC-V architecture in the field of cloud computing. Exploration of Virtualization Technology Based on BeiHai Cloud Computing Experimental Platform Exploration of Virtualization Technology Based on BeiHai Cloud Computing Experimental Platform Currently, the performance and ecosystem of RISC-V chips are limited, and the industry lacks a large-scale cloud computing cluster verification environment, which restricts the application and promotion of RISC-V in the field of cloud computing. In response to this issue, China Telecom Research Institute has launched the BeiHai RISC-V cloud computing experimental platform, which has built a complete solution based on hardware facilities such as RISC-V servers, TPU, VPU, and Kubernetes based application platforms. At present, the BeiHai platform has added RISC-V virtualization capabilities. In this speech, we will first introduce the BeiHai platform and the newly added hardware virtualization capabilities. Then, we will introduce KubeVirt adaptation based on the BeiHai platform. In the speech, we will introduce the methods and difficulties of adapting each component of KubeVirt to the RISC-V architecture, as well as the application exploration of building virtual machine and container resource pools based on RISC-V hardware, promoting the application of RISC-V architecture in the field of cloud computing.
Tianzheng Li
Researcher, China Telecom Research Institute
15:00 - 15:30 Tea Break
Tea Break
15:30 - 15:45 Golang on RISC-V: the Status and the Future Golang on RISC-V: the Status and the Future This topic will introduce the history of Golang and RISC-V, then describe the current status from aspects such as the support of RISC-V extensions, compiler, core tools, development tools, third-party applications, and community developers, and finally look forward to the future RISC-V Golang. Golang on RISC-V: the Status and the Future Golang on RISC-V: the Status and the Future This topic will introduce the history of Golang and RISC-V, then describe the current status from aspects such as the support of RISC-V extensions, compiler, core tools, development tools, third-party applications, and community developers, and finally look forward to the future RISC-V Golang.
Pengcheng Wang
Compiler Engineer, ByteDance
Meng Zhuo
RISC-V Developer, ISCAS
15:45 - 16:00 V8 for RISC-V One-Year Progress: What's New V8 for RISC-V One-Year Progress: What's New As the entry point for web applications, browsers hold a critical technical position. Their importance in establishing the completeness of RISC-V software ecosystems cannot be overstated.
• Currently, Google Chrome dominates the browser market, and Chromium is the open-source project for Chrome. V8 is the JavaScript engine in Chromium, which was listed as "Help Wanted" as early as 2019 in the RVI's GitHub riscv-software-list page.
• PLCT lab started V8’s port at the beginning of 2020. Since its upstream at early 2021, PLCT Lab have maintained it for over 4 years. Huge efforts have been paid to ensuring the functional completeness and performance usability of V8 for RISC-V.
• The work had been done in 2024 will be introduced. 		V8 for RISC-V One-Year Progress: What's New V8 for RISC-V One-Year Progress: What's New As the entry point for web applications, browsers hold a critical technical position. Their importance in establishing the completeness of RISC-V software ecosystems cannot be overstated.
• Currently, Google Chrome dominates the browser market, and Chromium is the open-source project for Chrome. V8 is the JavaScript engine in Chromium, which was listed as "Help Wanted" as early as 2019 in the RVI's GitHub riscv-software-list page.
• PLCT lab started V8’s port at the beginning of 2020. Since its upstream at early 2021, PLCT Lab have maintained it for over 4 years. Huge efforts have been paid to ensuring the functional completeness and performance usability of V8 for RISC-V.
• The work had been done in 2024 will be introduced.
Yahan Lu
Compiler Engineer, PLCT Lab, Institute of Software, Chinese Academy of Sciences
16:00 - 16:15 Optimizing Audio Algorithms on RISC-V Architecture Optimizing Audio Algorithms on RISC-V Architecture RISC-V's rise in embedded/IoT drives demand for audio processing. While audio requires high performance and low power, RISC-V lacks mature audio algorithm libraries unlike x86, ARM, or DSPs.
The Nuclei Audio Library addresses this, optimized for RISC-V (especially Nuclei CPUs). It offers a comprehensive, bare-metal, high-performance solution by integrating and optimizing open-source algorithms for RISC-V.
Algorithm support includes: Speech Codecs (AMR-WB, Opus, LC3plus), General Audio Codecs (MP3, SBC), and Speech Enhancement (SpeexDSP-based AEC, NS, AGC).
Optimization strategies: Performance Profiling (Nuclei Studio IDE) for bottlenecks; Hardware Acceleration (Nuclei N3 DSP & zilsd extensions) for enhanced RV32 computation & memory access; RISC-V Vector (V) Extension for parallel processing (FFT, filters), boosting throughput.
The Nuclei Audio Library gives RISC-V efficient, ready-to-use audio processing, filling a key gap for smart assistants, wearables, and IoT. Future plans: expand algorithms (AI speech enhancement, sound recognition) and optimize for new extensions. 		Optimizing Audio Algorithms on RISC-V Architecture Optimizing Audio Algorithms on RISC-V Architecture RISC-V's rise in embedded/IoT drives demand for audio processing. While audio requires high performance and low power, RISC-V lacks mature audio algorithm libraries unlike x86, ARM, or DSPs.
The Nuclei Audio Library addresses this, optimized for RISC-V (especially Nuclei CPUs). It offers a comprehensive, bare-metal, high-performance solution by integrating and optimizing open-source algorithms for RISC-V.
Algorithm support includes: Speech Codecs (AMR-WB, Opus, LC3plus), General Audio Codecs (MP3, SBC), and Speech Enhancement (SpeexDSP-based AEC, NS, AGC).
Optimization strategies: Performance Profiling (Nuclei Studio IDE) for bottlenecks; Hardware Acceleration (Nuclei N3 DSP & zilsd extensions) for enhanced RV32 computation & memory access; RISC-V Vector (V) Extension for parallel processing (FFT, filters), boosting throughput.
The Nuclei Audio Library gives RISC-V efficient, ready-to-use audio processing, filling a key gap for smart assistants, wearables, and IoT. Future plans: expand algorithms (AI speech enhancement, sound recognition) and optimize for new extensions.
Jiandong Qiu
Foundational Software Engineer, Nuclei
16:15 - 16:30 Introduce the implementation of LLVM Loop Vectorizer Introduce the implementation of LLVM Loop Vectorizer This talk focuses on the LLVM autovectorization implementation. It includes the basic introduction of VPlan, the current development status and the future Roadmap, as well as the key features such as VP IR which are more related to RISC-V. Finally, shows some performance test data and code examples that need to be improved Introduce the implementation of LLVM Loop Vectorizer Introduce the implementation of LLVM Loop Vectorizer This talk focuses on the LLVM autovectorization implementation. It includes the basic introduction of VPlan, the current development status and the future Roadmap, as well as the key features such as VP IR which are more related to RISC-V. Finally, shows some performance test data and code examples that need to be improved
Liqin Weng
Compiler Expert, SpacemiT
16:30 - 16:45 RISC-V Unified Database RISC-V Unified Database The RISC-V Unified Database (UDB) is a transformative initiative aimed at consolidating the fragmented RISC-V specification into a single, machine-readable source of truth. As the ecosystem expands with nearly 200 ratified extensions, UDB addresses critical challenges in consistency, traceability, and automation. It enables the generation of ISA manuals, instruction indices, and simulators directly from structured YAML data, reducing duplication and error. This session will explore UDB’s architecture, current capabilities, and roadmap, highlighting its potential to become the foundation for the next generation of RISC-V tooling and documentation. Community participation is encouraged to help shape this open, collaborative effort. RISC-V Unified Database RISC-V Unified Database The RISC-V Unified Database (UDB) is a transformative initiative aimed at consolidating the fragmented RISC-V specification into a single, machine-readable source of truth. As the ecosystem expands with nearly 200 ratified extensions, UDB addresses critical challenges in consistency, traceability, and automation. It enables the generation of ISA manuals, instruction indices, and simulators directly from structured YAML data, reducing duplication and error. This session will explore UDB’s architecture, current capabilities, and roadmap, highlighting its potential to become the foundation for the next generation of RISC-V tooling and documentation. Community participation is encouraged to help shape this open, collaborative effort.
Afonso Oliveira
Senior Software Engineer, Synopsys
16:45 - 17:00 Enabling Native Library Support for QEMU-User on RISC-V Enabling Native Library Support for QEMU-User on RISC-V RISC-V is gaining attention as a new ISA, but it lacks application support compared to x86 and ARM. Binary translation helps solve this problem, but QEMU-user has poor performance due to TCG limitations. Box64 performs better by using native libraries, but requires manual work to create library wrappers.
We solve this by using QEMU's existing syscall interception with lightweight guest stubs to call host libraries directly. This creates an automated, one-button solution for wrapping host libraries without manual coding. 		Enabling Native Library Support for QEMU-User on RISC-V Enabling Native Library Support for QEMU-User on RISC-V RISC-V is gaining attention as a new ISA, but it lacks application support compared to x86 and ARM. Binary translation helps solve this problem, but QEMU-user has poor performance due to TCG limitations. Box64 performs better by using native libraries, but requires manual work to create library wrappers.
We solve this by using QEMU's existing syscall interception with lightweight guest stubs to call host libraries directly. This creates an automated, one-button solution for wrapping host libraries without manual coding.
Yun Wang
PhD Candidate, Shanghai Jiao Tong University
17:00 - 17:15 rv64.zip: Unifying Diverse RISC-V ISA Ecosystem rv64.zip: Unifying Diverse RISC-V ISA Ecosystem RISC-V extensions provide substantial performance improvements but are inconsistently supported across processors, complicating software distribution. Most binaries are compiled for the base RV64GC ISA today, leaving potential performance gains unutilized. This project introduces a function-level target clone table, generated automatically using a PGO-based approach, to clone function implementations based on available extensions while maintaining RV64GC compatibility. Evaluation on SPECCPU 2006 benchmarks demonstrated a speedup of up to 2.05x in hmmer. An 8.4% geometric mean improvement over all possible extensions RV64GCBV_Zicond, achieved by excluding extensions that degrade performance. We generated only 55 functions with clones across the entire benchmark suite, ensuring a compact binary. This solution streamlines development, maximizes hardware efficiency, and simplifies software distribution across diverse RISC-V platforms. rv64.zip: Unifying Diverse RISC-V ISA Ecosystem rv64.zip: Unifying Diverse RISC-V ISA Ecosystem RISC-V extensions provide substantial performance improvements but are inconsistently supported across processors, complicating software distribution. Most binaries are compiled for the base RV64GC ISA today, leaving potential performance gains unutilized. This project introduces a function-level target clone table, generated automatically using a PGO-based approach, to clone function implementations based on available extensions while maintaining RV64GC compatibility. Evaluation on SPECCPU 2006 benchmarks demonstrated a speedup of up to 2.05x in hmmer. An 8.4% geometric mean improvement over all possible extensions RV64GCBV_Zicond, achieved by excluding extensions that degrade performance. We generated only 55 functions with clones across the entire benchmark suite, ensuring a compact binary. This solution streamlines development, maximizes hardware efficiency, and simplifies software distribution across diverse RISC-V platforms.
Yangyu Chen
PhD Student, Chongqing University
Intern, Beijing Institute of Open Source Chip
17:15 - 17:30 Deploying openEuler RISC-V Everywhere: Adoption of Diversified Hardware Platforms The openEuler RISC-V team is carrying out systematic support work covering three major phases of the embedded board lifecycle: adaptation, validation, and application deployment. While continuously expanding supported board platforms, the team leverages diversified hardware solutions and reliable infrastructure to achieve comprehensive RISC-V software ecosystem monitoring capabilities. Deploying openEuler RISC-V Everywhere: Adoption of Diversified Hardware Platforms The openEuler RISC-V team is carrying out systematic support work covering three major phases of the embedded board lifecycle: adaptation, validation, and application deployment. While continuously expanding supported board platforms, the team leverages diversified hardware solutions and reliable infrastructure to achieve comprehensive RISC-V software ecosystem monitoring capabilities.
Hangfan Li
OS Engineer, Institute of Software, Chinese Academy of Sciences
Embedded System
Host:
Xiaoqing He Secretary General, Embedded Systems Association Director, China Software Industry AssociationPuxiang Xiong Founder and CEO, RT-Thread Chairman, Shanghai Open-Source Information Technology Association
7/18 9:00-12:00
Room 305
Time Title SpeakerTitle & Speaker
09:00 - 09:15 RISC-V Is Thriving, Diversify the Chip Ecosystem RISC-V Is Thriving, Diversify the Chip Ecosystem
RISC-V Is Thriving, Diversify the Chip Ecosystem RISC-V Is Thriving, Diversify the Chip Ecosystem
Frank Xu
Principal Analyst, Informa TechTarget
09:15 - 09:30 High-Determinism Real-Time RISC-V CPU with Functional Safety Features High-Determinism Real-Time RISC-V CPU with Functional Safety Features
High-Determinism Real-Time RISC-V CPU with Functional Safety Features High-Determinism Real-Time RISC-V CPU with Functional Safety Features
Xiaogeng Wang
Head of the Processor Department, ESWIN Computing
09:30 - 09:45 GS32-DSP Based on Nuclei RISC-V IP: A Technology Share for Domestic Replacement GS32-DSP Based on Nuclei RISC-V IP: A Technology Share for Domestic Replacement GS32-DSP series is deeply customized based on the Nuclei RISC-V IP, aligning with the national initiative to promote and develop the RISC-V ecosystem. It integrates a hybrid signal processing unit and a real-time control algorithm accelerator, featuring fully independent and controllable intellectual property rights. GS32-DSP Based on Nuclei RISC-V IP: A Technology Share for Domestic Replacement GS32-DSP Based on Nuclei RISC-V IP: A Technology Share for Domestic Replacement GS32-DSP series is deeply customized based on the Nuclei RISC-V IP, aligning with the national initiative to promote and develop the RISC-V ecosystem. It integrates a hybrid signal processing unit and a real-time control algorithm accelerator, featuring fully independent and controllable intellectual property rights.
Alex Chen
CEO, Gejian Semiconductor
09:45 - 10:00 RISC-V Based SoC Platform Integrating GNSS and BLE Technologies RISC-V Based SoC Platform Integrating GNSS and BLE Technologies In this session, Verislicon’s SoC platform based-on RISC-V cores is introduced, with GNSS and BLE technologies integrated for high performance and low power features. For high-precision GNSS, high performance RISC-V core is used for real-time signal processing in satellite tracking and intensive math computing in RTK, with optimal power consumption. For Bluetooth Low Energy, a compact RISC-V core is used for controller and stack software to implement ultra-low-power for sensor data transferring. Along with Verisilicon’s excellent BLE and GNSS RF IPs on FD-SOI 22nm process, the SoC platform can offer suitable solutions for applications in smart wearing, smart traffic and auto navigation etc. RISC-V Based SoC Platform Integrating GNSS and BLE Technologies RISC-V Based SoC Platform Integrating GNSS and BLE Technologies In this session, Verislicon’s SoC platform based-on RISC-V cores is introduced, with GNSS and BLE technologies integrated for high performance and low power features. For high-precision GNSS, high performance RISC-V core is used for real-time signal processing in satellite tracking and intensive math computing in RTK, with optimal power consumption. For Bluetooth Low Energy, a compact RISC-V core is used for controller and stack software to implement ultra-low-power for sensor data transferring. Along with Verisilicon’s excellent BLE and GNSS RF IPs on FD-SOI 22nm process, the SoC platform can offer suitable solutions for applications in smart wearing, smart traffic and auto navigation etc.
Yi Zeng
Senior Director, Wireless IP Platform, VeriSilicon
10:00 - 10:15 RISC-V-Based, BLE-Integrated Ultra-Low-Power MCU and Its Smart Healthcare Applications RISC-V is increasingly being adopted in a wide range of products due to its open platform and streamlined instruction set. This presentation introduces a BLE MCU chip based on the domestic RISC-V architecture, which integrates BLE into the SoC to achieve ultra-low power consumption, as well as its applications in the digital health field. RISC-V-Based, BLE-Integrated Ultra-Low-Power MCU and Its Smart Healthcare Applications RISC-V is increasingly being adopted in a wide range of products due to its open platform and streamlined instruction set. This presentation introduces a BLE MCU chip based on the domestic RISC-V architecture, which integrates BLE into the SoC to achieve ultra-low power consumption, as well as its applications in the digital health field.
Tingting Gao
R&D Director, VeriSyno
10:15 - 10:45 Tea Break
Tea Break
10:45 - 11:00 Scaling RISC-V Performance: Multicore RTOS for Real-Time Demands Scaling RISC-V Performance: Multicore RTOS for Real-Time Demands I. Opportunities and Challenges of RISC-V in the Current Era
Evolution and Strategic Significance of the RISC-V Architecture
Key Opportunities and Challenges Facing RISC-V
II. Advancing RISC-V Development Through Industrial Ecosystems
Accelerating RISC-V Ecosystem Building via the Operating System
Case Sharing on RISC-V Chip Deployment
Case Sharing on RISC-V Ecosystem Development
III. Future Prospects for RISC-V
OS-Related Technical Advantages and Innovations of RISC-V Architecture
Ecosystem Development Pathways
Market Outlook 		Scaling RISC-V Performance: Multicore RTOS for Real-Time Demands Scaling RISC-V Performance: Multicore RTOS for Real-Time Demands I. Opportunities and Challenges of RISC-V in the Current Era
Evolution and Strategic Significance of the RISC-V Architecture
Key Opportunities and Challenges Facing RISC-V
II. Advancing RISC-V Development Through Industrial Ecosystems
Accelerating RISC-V Ecosystem Building via the Operating System
Case Sharing on RISC-V Chip Deployment
Case Sharing on RISC-V Ecosystem Development
III. Future Prospects for RISC-V
OS-Related Technical Advantages and Innovations of RISC-V Architecture
Ecosystem Development Pathways
Market Outlook
Puxiang Xiong
Founder and CEO, RT-Thread Chairman, Shanghai Open-Source Information Technology Association
11:00 - 11:15 The Evolution of HPMicro High-Performance MCUs in Robotic Motion Control The Evolution of HPMicro High-Performance MCUs in Robotic Motion Control As robotic systems become more complex and performance-intensive, the demands on embedded control platforms continue to rise. In this session, we’ll explore how HPMicro’s high-performance RISC-V MCU series—HPM6E00 and HPM5300—are addressing critical challenges in robotic motion control, including compute efficiency, power optimization, low-latency communication, and system-level integration.
With native EtherCAT support, high-resolution PWM capabilities, and a compact yet powerful architecture, HPMicro's MCUs are empowering next-generation joint servo and dexterous hand systems—driving robotic motion toward higher precision, faster response, and greater integration flexibility.
Join us to see how HPMicro RISC-V innovation is shaping the future of robotics. 		The Evolution of HPMicro High-Performance MCUs in Robotic Motion Control The Evolution of HPMicro High-Performance MCUs in Robotic Motion Control As robotic systems become more complex and performance-intensive, the demands on embedded control platforms continue to rise. In this session, we’ll explore how HPMicro’s high-performance RISC-V MCU series—HPM6E00 and HPM5300—are addressing critical challenges in robotic motion control, including compute efficiency, power optimization, low-latency communication, and system-level integration.
With native EtherCAT support, high-resolution PWM capabilities, and a compact yet powerful architecture, HPMicro's MCUs are empowering next-generation joint servo and dexterous hand systems—driving robotic motion toward higher precision, faster response, and greater integration flexibility.
Join us to see how HPMicro RISC-V innovation is shaping the future of robotics.
Jintao Zeng
Founder and CEO, HPMicro
11:15 - 11:30 How to Elevate the Security Level of RISC-V Based SoC Designs with a RISC-V Based Root-of-Trust How to Elevate the Security Level of RISC-V Based SoC Designs with a RISC-V Based Root-of-Trust Rambus will provide an overview of how general-purpose RISC-V based compute subsystems can be extended with an integrated RISC-V based Root-of-Trust element or Hardware Security Module that provides security and cryptographic services to the platform. Such a Root-of-Trust element will ensure a hardware enforced trusted execution environment providing services like trusted and secure identity, secure lifecycle and configuration management, secure boot and firmware management, secure debug etc. Specific segments like automotive call for additional functional safety mechanisms, while others like data center call for higher protection levels offered by side channel attack (SCA) countermeasures and protection mechanisms. Future proofing security systems can be done through adding next generation quantum safe cryptographic accelerators. Rambus will demonstrate how to integrate the HW RTL level physical interfaces, the security firmware and middleware stack components. Finally, guidance is provided for the security and safety certification landscape. How to Elevate the Security Level of RISC-V Based SoC Designs with a RISC-V Based Root-of-Trust How to Elevate the Security Level of RISC-V Based SoC Designs with a RISC-V Based Root-of-Trust Rambus will provide an overview of how general-purpose RISC-V based compute subsystems can be extended with an integrated RISC-V based Root-of-Trust element or Hardware Security Module that provides security and cryptographic services to the platform. Such a Root-of-Trust element will ensure a hardware enforced trusted execution environment providing services like trusted and secure identity, secure lifecycle and configuration management, secure boot and firmware management, secure debug etc. Specific segments like automotive call for additional functional safety mechanisms, while others like data center call for higher protection levels offered by side channel attack (SCA) countermeasures and protection mechanisms. Future proofing security systems can be done through adding next generation quantum safe cryptographic accelerators. Rambus will demonstrate how to integrate the HW RTL level physical interfaces, the security firmware and middleware stack components. Finally, guidance is provided for the security and safety certification landscape.
Samuel Chiang
Business Development Director APAC, Rambus
11:30 - 11:45 Nuclei TEE: RISC-V Secure System Practice Nuclei TEE: RISC-V Secure System Practice # Nuclei TEE: RISC-V Secure System Practice
## Introduction to TEE
Introduces the basic concepts of TEE.
## Nuclei TEE Solution
Nuclei Technology has conducted research and exploration on TEE solutions for both AP-level and MCU-level CPUs.
### Nuclei Linux TEE Solution
For AP-level processors (similar to ARM Cortex-A55), we explored an implementation based on the OP-TEE open-source solution on the Nuclei UX900 platform.
We primarily leveraged existing hardware to achieve basic isolation:
- **Memory Isolation:**
- **CPU Secure State Isolation:**
- **Interrupt Isolation:**
### Nuclei MCU TEE Solution
For MCU-level processors (similar to ARM Cortex-M33), we explored an implementation based on the TFM (Trusted Firmware-M) open-source solution on the Nuclei N300 platform.
We similarly leveraged existing hardware to achieve basic isolation:
- **Memory Isolation:**
- **CPU Secure State Isolation:**
- **Interrupt Isolation:**
## Demo Examples
We will demonstrate examples of OP-TEE running the xtest and TFM running the tf-m-tests regression tests to validate the effectiveness of the NUCLEI TEE solution. 		Nuclei TEE: RISC-V Secure System Practice Nuclei TEE: RISC-V Secure System Practice # Nuclei TEE: RISC-V Secure System Practice
## Introduction to TEE
Introduces the basic concepts of TEE.
## Nuclei TEE Solution
Nuclei Technology has conducted research and exploration on TEE solutions for both AP-level and MCU-level CPUs.
### Nuclei Linux TEE Solution
For AP-level processors (similar to ARM Cortex-A55), we explored an implementation based on the OP-TEE open-source solution on the Nuclei UX900 platform.
We primarily leveraged existing hardware to achieve basic isolation:
- **Memory Isolation:**
- **CPU Secure State Isolation:**
- **Interrupt Isolation:**
### Nuclei MCU TEE Solution
For MCU-level processors (similar to ARM Cortex-M33), we explored an implementation based on the TFM (Trusted Firmware-M) open-source solution on the Nuclei N300 platform.
We similarly leveraged existing hardware to achieve basic isolation:
- **Memory Isolation:**
- **CPU Secure State Isolation:**
- **Interrupt Isolation:**
## Demo Examples
We will demonstrate examples of OP-TEE running the xtest and TFM running the tf-m-tests regression tests to validate the effectiveness of the NUCLEI TEE solution.
Bing Gui
Senior SW Engineer, Nuclei
11:45 - 12:00 Ecosystem-Driven Innovation: GPU and RISC-V Collaborating for Smarter Automotive Solutions Ecosystem-Driven Innovation: GPU and RISC-V Collaborating for Smarter Automotive Solutions 1. RISC-V has a lot of potential now and in the future, automotive is one of its target market.
2. IMG as GPU IP global leading provider, continues work closely with/contribute in RISC-V ecosystem
3. automotive computing: scalable, safe and open
4 automotive design points: flexibility , future workloads scoping, innovation for differentiation.
5. IMG GPU is essential for real time visualization , sensor fusion, display pipeline parallel AI workloads and safety-critical rendering.
6. Introduce IMG IP for auto compute and rendering request.
7. IMG works closely with ecosystem partners and RISC-V communities to enhance vertical cooperations for automotive market. 		Ecosystem-Driven Innovation: GPU and RISC-V Collaborating for Smarter Automotive Solutions Ecosystem-Driven Innovation: GPU and RISC-V Collaborating for Smarter Automotive Solutions 1. RISC-V has a lot of potential now and in the future, automotive is one of its target market.
2. IMG as GPU IP global leading provider, continues work closely with/contribute in RISC-V ecosystem
3. automotive computing: scalable, safe and open
4 automotive design points: flexibility , future workloads scoping, innovation for differentiation.
5. IMG GPU is essential for real time visualization , sensor fusion, display pipeline parallel AI workloads and safety-critical rendering.
6. Introduce IMG IP for auto compute and rendering request.
7. IMG works closely with ecosystem partners and RISC-V communities to enhance vertical cooperations for automotive market.
Yin Huang
Senior Business Development Manager, Imagination
Automotive Electronics
Host:
Bob Hu Founder, NucleiNing He Senior Vice President & CTO, ESWIN Computing
7/18 13:30-17:30
Room 305
Time Title SpeakerTitle & Speaker
13:30 - 13:45 Integrate into the RISC-V Ecosystem to Promote the Industrialization of Vehicle-Grade MCUs Integrate into the RISC-V Ecosystem to Promote the Industrialization of Vehicle-Grade MCUs With the risen of domestic new energy vehicles, the demand for independent and controllable MCUs has exploded. With more than ten years of technology and product accumulation in MCU field, Binary Semiconductor company actively embraces the RISC-V ecosystem and collaborate with multiple car companies and industry ecosystem partners to develop a fully domestically produced vehicle-grade MCU chips.
In this speech,we reviewed the development history of Binary Semiconductor company in the field of MCU technology,as well as the related product development and application promotion experiences. We will share some of our thoughts on the construction of the RISC-V ecosystem, as well as our practices in the development and application of vehicle-grade MCU chips. We hope to take this opportunity to build a broader ecological partner group and contribute to the industrialization of domestically produced automotive-grade MCU chips. 		Integrate into the RISC-V Ecosystem to Promote the Industrialization of Vehicle-Grade MCUs Integrate into the RISC-V Ecosystem to Promote the Industrialization of Vehicle-Grade MCUs With the risen of domestic new energy vehicles, the demand for independent and controllable MCUs has exploded. With more than ten years of technology and product accumulation in MCU field, Binary Semiconductor company actively embraces the RISC-V ecosystem and collaborate with multiple car companies and industry ecosystem partners to develop a fully domestically produced vehicle-grade MCU chips.
In this speech,we reviewed the development history of Binary Semiconductor company in the field of MCU technology,as well as the related product development and application promotion experiences. We will share some of our thoughts on the construction of the RISC-V ecosystem, as well as our practices in the development and application of vehicle-grade MCU chips. We hope to take this opportunity to build a broader ecological partner group and contribute to the industrialization of domestically produced automotive-grade MCU chips.
YongZhou Chen
CTO, Wuhan Binary Semiconductor Co., Ltd.
13:45 - 14:00 Intelligent Vehicle Enablement: ESWIN's RISC-V Automotive Computing Matrix with Integrated Safety Architecture ESWIN has built a RISC-V-based computing matrix covering full scenarios for automotive electronics, including:
In-vehicle computing & control (zone controllers): Supports RVV vector and Matrix acceleration (NPU) for AI inference and multi-modal fusion.
High-efficiency signal processing (body & powertrain): Integrates DSP/RVV instructions for optimized image processing and real-time control.
Ultra-low-power intelligent control (sensors & edge nodes): Combines HSM security and TMU motor acceleration.
Its integrated safety architecture supports functional safety (lockstep, anti-side-channel attacks) and cybersecurity (HSM), and is AUTOSAR-compliant.
Backed by domestic supply chain, automotive-grade process and RISC-V ecosystem, it enables Software Defined Vehicle (SDV).
This full-stack computing matrix powers the evolution of intelligent vehicles toward AI-driven architecture.
RISC-V offers strong advantages in automotive:
Enables custom instruction sets for autonomous driving and in-vehicle systems.
Modular design supports flexible extensions for AI acceleration and security encryption.
Efficient & low-power architecture meets real-time requirements of automotive ECUs.
Supports deep integration of hardware-based safety mechanisms, complying with ISO 26262.
A rapidly growing global ecosystem accelerates automotive adoption. 		Intelligent Vehicle Enablement: ESWIN's RISC-V Automotive Computing Matrix with Integrated Safety Architecture ESWIN has built a RISC-V-based computing matrix covering full scenarios for automotive electronics, including:
In-vehicle computing & control (zone controllers): Supports RVV vector and Matrix acceleration (NPU) for AI inference and multi-modal fusion.
High-efficiency signal processing (body & powertrain): Integrates DSP/RVV instructions for optimized image processing and real-time control.
Ultra-low-power intelligent control (sensors & edge nodes): Combines HSM security and TMU motor acceleration.
Its integrated safety architecture supports functional safety (lockstep, anti-side-channel attacks) and cybersecurity (HSM), and is AUTOSAR-compliant.
Backed by domestic supply chain, automotive-grade process and RISC-V ecosystem, it enables Software Defined Vehicle (SDV).
This full-stack computing matrix powers the evolution of intelligent vehicles toward AI-driven architecture.
RISC-V offers strong advantages in automotive:
Enables custom instruction sets for autonomous driving and in-vehicle systems.
Modular design supports flexible extensions for AI acceleration and security encryption.
Efficient & low-power architecture meets real-time requirements of automotive ECUs.
Supports deep integration of hardware-based safety mechanisms, complying with ISO 26262.
A rapidly growing global ecosystem accelerates automotive adoption.
Patrick Chen
Head of ABU MCU+ Development Center, ESWIN Computing
14:00 - 14:15 Functional Safety and Practice in Automotive Software Development Amid the intelligent transformation of the automotive industry, functional safety software has become a core pillar enabling trustworthy technology. The ISO 26262 standard embeds safety into the entire automotive software lifecycle through a structured framework:
Strategic Alignment
From hazard analysis at the concept stage (HARA) to system development, safety goals such as ASIL levels are deeply integrated with software requirements, ensuring that technological innovation does not compromise safety.
Industrial Collaboration
The standard mandates a closed-loop process covering hardware/software development, verification and validation, and supply chain management (e.g., component certification, reuse specifications), providing a unified safety language for OEMs and suppliers.
Technology Enablement
Through ASIL decomposition (e.g., de-rating via redundant design) and hierarchical monitoring mechanisms (e.g., Honda’s IMMD monitoring module), software serves as a critical enabler of functional resilience.
Business Value
Functional safety software is not only a compliance requirement but also a competitive differentiator for automakers. As vehicles evolve from traditional control (e.g., speed management) to new energy and autonomous driving, it forms the foundation of user trust and technical reliability. 		Functional Safety and Practice in Automotive Software Development Amid the intelligent transformation of the automotive industry, functional safety software has become a core pillar enabling trustworthy technology. The ISO 26262 standard embeds safety into the entire automotive software lifecycle through a structured framework:
Strategic Alignment
From hazard analysis at the concept stage (HARA) to system development, safety goals such as ASIL levels are deeply integrated with software requirements, ensuring that technological innovation does not compromise safety.
Industrial Collaboration
The standard mandates a closed-loop process covering hardware/software development, verification and validation, and supply chain management (e.g., component certification, reuse specifications), providing a unified safety language for OEMs and suppliers.
Technology Enablement
Through ASIL decomposition (e.g., de-rating via redundant design) and hierarchical monitoring mechanisms (e.g., Honda’s IMMD monitoring module), software serves as a critical enabler of functional resilience.
Business Value
Functional safety software is not only a compliance requirement but also a competitive differentiator for automakers. As vehicles evolve from traditional control (e.g., speed management) to new energy and autonomous driving, it forms the foundation of user trust and technical reliability.
Jun Sun
Vice President of Intelligent Drive Research Institute, ROXMOTOR
14:15 - 14:30 RISC-V-Based Automotive Security Framework RISC-V-Based Automotive Security Framework The automotive security threat landscape is rapidly worsening. The 2025 Global Automotive and Smart Mobility Cybersecurity Report highlights a significant increase in large-scale cyberattacks, impacting millions of mobility assets. The VicOne 2025 report attributes this to critical system vulnerabilities, especially in chipsets, which made up 50.9% of 2024’s reported issues, including backdoors and side-channel exploits. With an increasing regulatory focus on safety, resilience, and data protection, real-time responsiveness is vital, particularly for ASIL-D functions such as braking and steering. RISC-V offers a rich set of security tools—PMP, ePMP, xSPMP, xMTT, IOPMP, MMU, IOMMU—but not all are optimized for real-time automotive needs. This presentation examines current safety and security demands, assesses RISC-V’s suitability, and outlines how to configure these components for a secure, real-time automotive platform, with a focus on memory isolation, interrupt routing, and virtualization. RISC-V-Based Automotive Security Framework RISC-V-Based Automotive Security Framework The automotive security threat landscape is rapidly worsening. The 2025 Global Automotive and Smart Mobility Cybersecurity Report highlights a significant increase in large-scale cyberattacks, impacting millions of mobility assets. The VicOne 2025 report attributes this to critical system vulnerabilities, especially in chipsets, which made up 50.9% of 2024’s reported issues, including backdoors and side-channel exploits. With an increasing regulatory focus on safety, resilience, and data protection, real-time responsiveness is vital, particularly for ASIL-D functions such as braking and steering. RISC-V offers a rich set of security tools—PMP, ePMP, xSPMP, xMTT, IOPMP, MMU, IOMMU—but not all are optimized for real-time automotive needs. This presentation examines current safety and security demands, assesses RISC-V’s suitability, and outlines how to configure these components for a secure, real-time automotive platform, with a focus on memory isolation, interrupt routing, and virtualization.
Paul Ku
Deputy Director, Andes
14:30 - 14:45 Accelerating RISC-V Automotive Application Development: Challenges, Measures and IAR Practices As the demand for open and flexible instruction set architectures increases in the automotive industry, the application of RISC-V in vehicles is gradually expanding. However, automotive application development faces challenges such as increased hardware complexity, mismatch between software complexity and productivity, functional safety requirements, and the pressure of rapid delivery. To address these challenges, the development environment needs to support multi-supplier and multi-core systems, development tools need to be pre-certified to meet functional safety standards, proven mature development tools should be selected, and DevOps processes should be introduced to improve development efficiency and product quality. IAR, as a leading provider of embedded development solutions, offers a comprehensive suite of certified RISC-V development tools that can effectively support automotive application development and accelerate the adoption of RISC-V in the automotive industry. Accelerating RISC-V Automotive Application Development: Challenges, Measures and IAR Practices As the demand for open and flexible instruction set architectures increases in the automotive industry, the application of RISC-V in vehicles is gradually expanding. However, automotive application development faces challenges such as increased hardware complexity, mismatch between software complexity and productivity, functional safety requirements, and the pressure of rapid delivery. To address these challenges, the development environment needs to support multi-supplier and multi-core systems, development tools need to be pre-certified to meet functional safety standards, proven mature development tools should be selected, and DevOps processes should be introduced to improve development efficiency and product quality. IAR, as a leading provider of embedded development solutions, offers a comprehensive suite of certified RISC-V development tools that can effectively support automotive application development and accelerate the adoption of RISC-V in the automotive industry.
Brendan Pan
Senior Engineer, IAR Systems China
14:45 - 15:00 Automotive Basic Software Solution Based on RISC-V Architecture Introduce what automotive middleware is, how to support automotive middleware on RISC-V cores, including middleware such as real-time operating systems based on RISC-V cores, virtualization technology, information security firmware, etc. Specific instruction sets will be shared in detail, including how to implement it for RISC-V cores. Automotive Basic Software Solution Based on RISC-V Architecture Introduce what automotive middleware is, how to support automotive middleware on RISC-V cores, including middleware such as real-time operating systems based on RISC-V cores, virtualization technology, information security firmware, etc. Specific instruction sets will be shared in detail, including how to implement it for RISC-V cores.
Yanan Zhao
Automotive Base Software Expert, HiRain
15:00 - 15:15 Nuclei ASIL B/D RISC-V IP Automotive Implementation Challenges and Solutions The speech introduces the RISC-V CPU IP auto compliance methodology in Nuclei to achieve systematic ASIL-D and random hardware capability ASIL-B&D. The random hardware capability for different ASIL customers mainly depends on Nuclei self-developed HW/SW mechanisms. The speech also shares the challenges and solutions where Nuclei automotive customers integrate RISC-V IP to achieve automotive-grade ICs, which include Radar, Lidar, GNSS, MCU and etc. Nuclei ASIL B/D RISC-V IP Automotive Implementation Challenges and Solutions The speech introduces the RISC-V CPU IP auto compliance methodology in Nuclei to achieve systematic ASIL-D and random hardware capability ASIL-B&D. The random hardware capability for different ASIL customers mainly depends on Nuclei self-developed HW/SW mechanisms. The speech also shares the challenges and solutions where Nuclei automotive customers integrate RISC-V IP to achieve automotive-grade ICs, which include Radar, Lidar, GNSS, MCU and etc.
Tianbin Fan
Automotive Product Manager, Nuclei
15:15 - 15:45 Tea Break
Tea Break
15:45 - 16:00 EasyXMen Support the Development of RISC-V Hardware and Software Collaborative Ecosystem EasyXMen Support the Development of RISC-V Hardware and Software Collaborative Ecosystem With the development of automotive intelligence and electrification, vehicle operating systems are evolving toward platformization and integration, featuring higher complexity, greater development challenges, and increased R&D investments. The open-source model, with its unique advantage of optimizing the allocation of software development resources, has opened up new paths for technological breakthroughs and industrial upgrading in the automotive industry. iSOFT has open-sourced the intelligent driving operating system microkernel EasyAda and the Safety Vehicle Control Operating System EasyXMen for the industry, filling gaps in the open-source field of domestic vehicle operating systems. As iSOFT open-source vehicle operating systems deeply integrate with RISC-V, they will further accelerate the formation of an open ecosystem in the automotive industry, driving the adoption of more open-source software and RISC-V chips in vehicles. We look forward to more enterprises in the industry joining the open-source collaboration! EasyXMen Support the Development of RISC-V Hardware and Software Collaborative Ecosystem EasyXMen Support the Development of RISC-V Hardware and Software Collaborative Ecosystem With the development of automotive intelligence and electrification, vehicle operating systems are evolving toward platformization and integration, featuring higher complexity, greater development challenges, and increased R&D investments. The open-source model, with its unique advantage of optimizing the allocation of software development resources, has opened up new paths for technological breakthroughs and industrial upgrading in the automotive industry. iSOFT has open-sourced the intelligent driving operating system microkernel EasyAda and the Safety Vehicle Control Operating System EasyXMen for the industry, filling gaps in the open-source field of domestic vehicle operating systems. As iSOFT open-source vehicle operating systems deeply integrate with RISC-V, they will further accelerate the formation of an open ecosystem in the automotive industry, driving the adoption of more open-source software and RISC-V chips in vehicles. We look forward to more enterprises in the industry joining the open-source collaboration!
Xiaoxian Zhang
Deputy General Manager of iSOFT, President of iSOFT Strategic Research Institute
16:00 - 16:15 An Introduction to a Configurable High-Performance Automotive Domain Controller With automotive intelligence upgrades, traditional distributed E/E architectures face complexity and scalability issues due to low-speed bus interconnection of dozens of ECUs. Domain Control Units (DCUs) integrate multiple ECU functions into a SoC, centralizing computing power and reducing costs. However, increased system complexity raises fault propagation risks — a single failure may trigger cascading software-hardware failures.
Hardware virtualization creates isolated environments, enabling each ECU’s OS and functionality to run independently as virtual machines, enhancing reliability while meeting ISO 26262 functional safety requirements.
For real-time embedded scenarios like DCUs, Type-1 hypervisors are commonly used, running directly on hardware to manage CPU, memory, and task scheduling. With hardware-assisted virtualization, the hypervisor achieves CPU time-slot isolation, memory protection, and peripheral access control, blocking unauthorized operations and establishing secure boundaries for integrated systems. 		An Introduction to a Configurable High-Performance Automotive Domain Controller With automotive intelligence upgrades, traditional distributed E/E architectures face complexity and scalability issues due to low-speed bus interconnection of dozens of ECUs. Domain Control Units (DCUs) integrate multiple ECU functions into a SoC, centralizing computing power and reducing costs. However, increased system complexity raises fault propagation risks — a single failure may trigger cascading software-hardware failures.
Hardware virtualization creates isolated environments, enabling each ECU’s OS and functionality to run independently as virtual machines, enhancing reliability while meeting ISO 26262 functional safety requirements.
For real-time embedded scenarios like DCUs, Type-1 hypervisors are commonly used, running directly on hardware to manage CPU, memory, and task scheduling. With hardware-assisted virtualization, the hypervisor achieves CPU time-slot isolation, memory protection, and peripheral access control, blocking unauthorized operations and establishing secure boundaries for integrated systems.
Weili Li
CPU Architect at XuanTie Team, Alibaba DAMO Academy
16:15 - 16:30 HighTec Helps Rapid Development of RISC-V Automotive MCUs HighTec Helps Rapid Development of RISC-V Automotive MCUs Introducing HighTec's basic information and main products, HighTec's support for Risc-V series IP, instruction support, and compiler products. Introduction of HighTec's solution for compiler functional safety, and outlook and summary of the development of RISC-V automotive MCUs. HighTec Helps Rapid Development of RISC-V Automotive MCUs HighTec Helps Rapid Development of RISC-V Automotive MCUs Introducing HighTec's basic information and main products, HighTec's support for Risc-V series IP, instruction support, and compiler products. Introduction of HighTec's solution for compiler functional safety, and outlook and summary of the development of RISC-V automotive MCUs.
Jihui Wen
CTO, HighTec CN
16:30 - 16:45 RISC-V Automotive-Grade Compiler: Challenges and Solutions RISC-V Automotive-Grade Compiler: Challenges and Solutions The RISC-V architecture, with its flexibility and open, has garnered significant attention in the automotive industry. Many RISC-V IP vendors have released a range of automotive-grade IPs, which have been adopted by several automotive chip manufacturers. In automotive software development, compiler, as a vital bridge between hardware and software, the use of compiler must ensure that no additional risks affecting system safety are introduced. The open-source compilers commonly used by RISC-V developers often only address usability, falling short in high performance, safety and reliability. Thus, to promote the widespread adoption of RISC-V in the automotive industry, automotive-grade RISC-V compilers need to overcome challenges in usability, high performance, safety and reliability.
Given the current state of affairs, this presentation will delve into challenges confronted by RISC-V automotive-grade compilers: the completeness and scalability of instruction support, the performance of the compiler, approaches to ensuring functional safety.
Then, the presentation will propose solutions to these challenges and finally showcase the specific implementation and application effects. 		RISC-V Automotive-Grade Compiler: Challenges and Solutions RISC-V Automotive-Grade Compiler: Challenges and Solutions The RISC-V architecture, with its flexibility and open, has garnered significant attention in the automotive industry. Many RISC-V IP vendors have released a range of automotive-grade IPs, which have been adopted by several automotive chip manufacturers. In automotive software development, compiler, as a vital bridge between hardware and software, the use of compiler must ensure that no additional risks affecting system safety are introduced. The open-source compilers commonly used by RISC-V developers often only address usability, falling short in high performance, safety and reliability. Thus, to promote the widespread adoption of RISC-V in the automotive industry, automotive-grade RISC-V compilers need to overcome challenges in usability, high performance, safety and reliability.
Given the current state of affairs, this presentation will delve into challenges confronted by RISC-V automotive-grade compilers: the completeness and scalability of instruction support, the performance of the compiler, approaches to ensuring functional safety.
Then, the presentation will propose solutions to these challenges and finally showcase the specific implementation and application effects.
Can Hu
CMO, Terapines Technology
16:45 - 17:00 RISC-V Based Virtual Prototype, Accelerate Auto Software Development RISC-V Based Virtual Prototype, Accelerate Auto Software Development By leveraging Riscv standard VP, we could create virtual prototype environment easily for automotive Tier1 and OEM. Through the colloboration with toolchains, Riscv VP together with FPGA prototype could bring developers on board smoothly and save the time to develop software. RISC-V Based Virtual Prototype, Accelerate Auto Software Development RISC-V Based Virtual Prototype, Accelerate Auto Software Development By leveraging Riscv standard VP, we could create virtual prototype environment easily for automotive Tier1 and OEM. Through the colloboration with toolchains, Riscv VP together with FPGA prototype could bring developers on board smoothly and save the time to develop software.
Tieyang Wu
Co-founder, IDEON Representative, MachineWare China
17:00 - 17:15 RISC-V Architecture Enable Self-reliance in Smart Vehicle Chips RISC-V Architecture Enable Self-reliance in Smart Vehicle Chips 1.Industry landscape：exponential growth in smart vehicle semiconductor and localization breakthroughs.
2.Disruptive strategy：cercis semiconductor unique value proposition.
3.Product in practice：the RISC-V implementation path from R&D to Mass production.
4.Ecosystem collaboration ：standardization & industry chain co-innovation.
RISC-V Architecture Enable Self-reliance in Smart Vehicle Chips RISC-V Architecture Enable Self-reliance in Smart Vehicle Chips
1.Industry landscape：exponential growth in smart vehicle semiconductor and localization breakthroughs.
2.Disruptive strategy：cercis semiconductor unique value proposition.
3.Product in practice：the RISC-V implementation path from R&D to Mass production.
4.Ecosystem collaboration ：standardization & industry chain co-innovation.
Changfeng Cao
Chairman of Cercis-Semi
17:15 - 17:30 RISC-V in Vehicles: Reshaping Software-defined Vehicles with an Open Ecosystem RISC-V in Vehicles: Reshaping Software-defined Vehicles with an Open Ecosystem At present, the automotive industry is undergoing a dual revolution of "software-defined" and "chip autonomy". RISC-V, with its three core advantages of open source instruction set, flexible customization and geopolitical security, has become the key path to break the predicament of "lacking chips and souls" in China's automotive industry. However, the application of RISC-V in vehicles is by no means a single-point chip replacement, but rather an ecological-level collaborative systems engineering.
Regarding how the current RISC-V software ecosystem can meet the requirements of automotive regulations and achieve rapid mass production, keynote speeches will be conducted from the following three aspects:
1.The technical advantages and application scenarios of RISC-V in the automotive field.
2.The collaboration challenges in the automotive software ecosystem and the solutions brought by RISC-V, including software-hardware decoupling architecture, and standardized toolchains
3.The RISC-V platform builds a collaborative model for the future automotive software ecosystem, including the role positioning and cooperation mechanisms of Oems, Tier1 suppliers, and chip manufacturers 		RISC-V in Vehicles: Reshaping Software-defined Vehicles with an Open Ecosystem RISC-V in Vehicles: Reshaping Software-defined Vehicles with an Open Ecosystem At present, the automotive industry is undergoing a dual revolution of "software-defined" and "chip autonomy". RISC-V, with its three core advantages of open source instruction set, flexible customization and geopolitical security, has become the key path to break the predicament of "lacking chips and souls" in China's automotive industry. However, the application of RISC-V in vehicles is by no means a single-point chip replacement, but rather an ecological-level collaborative systems engineering.
Regarding how the current RISC-V software ecosystem can meet the requirements of automotive regulations and achieve rapid mass production, keynote speeches will be conducted from the following three aspects:
1.The technical advantages and application scenarios of RISC-V in the automotive field.
2.The collaboration challenges in the automotive software ecosystem and the solutions brought by RISC-V, including software-hardware decoupling architecture, and standardized toolchains
3.The RISC-V platform builds a collaborative model for the future automotive software ecosystem, including the role positioning and cooperation mechanisms of Oems, Tier1 suppliers, and chip manufacturers
John Zhang
Vice President, Shanghai Zhicong
EDA
Host:
Xiaozhong Wu Vice President, UniVistaYingren Chen Vice President, S2C
7/18 9:00-12:30
Room 302
Time Title SpeakerTitle & Speaker
09:00 - 09:20 SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification The RISC-V open instruction set has accelerated the development of domain-specific custom processors and microarchitectures.
The growing diversity of novel microarchitectures calls for efficient performance evaluation tools to enable rapid iterative development.
Our work focuses on two key aspects:
(1) a cycle-accurate microarchitecture modeling approach and simulation tool that enables accurate assessment of RTL modifications on final processor performance during rapid design iterations;
and (2) a user-mode (syscall-mode) simulation method targeting RTL or RTL-like models, which allows direct execution of multi-process user-space Linux target programs and performance profiling without the need for full SoC integration or target software stack adaptation.
We have validated our system with a functional demo and released it as open source.
Experimental results show that our tool achieves over 97% accuracy in simulating target hardware performance (in cycle count) and delivers simulation speeds more than 5× faster than Verilator-based full-system RTL simulation. 		SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification The RISC-V open instruction set has accelerated the development of domain-specific custom processors and microarchitectures.
The growing diversity of novel microarchitectures calls for efficient performance evaluation tools to enable rapid iterative development.
Our work focuses on two key aspects:
(1) a cycle-accurate microarchitecture modeling approach and simulation tool that enables accurate assessment of RTL modifications on final processor performance during rapid design iterations;
and (2) a user-mode (syscall-mode) simulation method targeting RTL or RTL-like models, which allows direct execution of multi-process user-space Linux target programs and performance profiling without the need for full SoC integration or target software stack adaptation.
We have validated our system with a functional demo and released it as open source.
Experimental results show that our tool achieves over 97% accuracy in simulating target hardware performance (in cycle count) and delivers simulation speeds more than 5× faster than Verilator-based full-system RTL simulation.
Yinan Xu
Special Research Assistant, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)
Special Research Assistant, Beijing Institute of Open Source Chip
09:20 - 09:40 Large-Scale FPGA Prototyping Methodology for Multi-Core High-Performance RISC-V Processors Large-Scale FPGA Prototyping Methodology for Multi-Core High-Performance RISC-V Processors This presentation introduces the architecture of the X200, a high-performance RISC-V core designed for data centers, detailing the functional features of its key components. It also covers the innovative and scalable interconnect bus designed for communication between cores Large-Scale FPGA Prototyping Methodology for Multi-Core High-Performance RISC-V Processors Large-Scale FPGA Prototyping Methodology for Multi-Core High-Performance RISC-V Processors This presentation introduces the architecture of the X200, a high-performance RISC-V core designed for data centers, detailing the functional features of its key components. It also covers the innovative and scalable interconnect bus designed for communication between cores
Mengxia Cao
Verification Product Line Marketing Director, UniVista
09:40 - 10:00 Tessent UltraSight-V: An On-chip Debug and Trace Solution for RISC-V Systems Tessent UltraSight-V: An On-chip Debug and Trace Solution for RISC-V Systems
Tessent UltraSight-V: An On-chip Debug and Trace Solution for RISC-V Systems Tessent UltraSight-V: An On-chip Debug and Trace Solution for RISC-V Systems
Yifan Li
Account Technology Manager, SIEMENS EDA
10:00 - 10:20 Nuclei Model:基于 System C 的 Near Cycle Model
Nuclei Model:基于 System C 的 Near Cycle Model
Zitai Xu
Technology Modeling Engineer, Nuclei
10:20 - 10:50 Tea Break
Tea Break
10:50 - 11:10 Accelerating Custom RISC-V Instruction Development with Andes' ACE Framework and AndesCycle Accelerating Custom RISC-V Instruction Development with Andes' ACE Framework and AndesCycle The open and extensible nature of RISC-V has fueled innovation across various computational domains. However, designing custom instruction set extensions remains technically demanding and time-consuming. Andes Technology created the ACE (Andes Custom Extension) framework with its COPILOT (Custom-OPtimized Instruction deveLOpment Tools) design tool to tackle this problem. To further enhance the ACE framework, AndesCycle—a cycle-accurate simulator with ACE support—has been introduced. AndesCycle allows designers to create precise, cycle-accurate model of custom instructions through C/C++ programming within ACE framework. This software-centric methodology removes RTL design barriers while providing access to extensive software libraries like SoftFloat, significantly reducing the cost of early-stage exploration. This talk will present two case studies that illustrate how these software tools accelerate custom instruction design: An RVV extension, inspired by a ByteDance proposal, designed to accelerate video codec processing. An RVV extension optimized for element-wise kernel functions frequently used in AI workloads. Accelerating Custom RISC-V Instruction Development with Andes' ACE Framework and AndesCycle Accelerating Custom RISC-V Instruction Development with Andes' ACE Framework and AndesCycle The open and extensible nature of RISC-V has fueled innovation across various computational domains. However, designing custom instruction set extensions remains technically demanding and time-consuming. Andes Technology created the ACE (Andes Custom Extension) framework with its COPILOT (Custom-OPtimized Instruction deveLOpment Tools) design tool to tackle this problem. To further enhance the ACE framework, AndesCycle—a cycle-accurate simulator with ACE support—has been introduced. AndesCycle allows designers to create precise, cycle-accurate model of custom instructions through C/C++ programming within ACE framework. This software-centric methodology removes RTL design barriers while providing access to extensive software libraries like SoftFloat, significantly reducing the cost of early-stage exploration. This talk will present two case studies that illustrate how these software tools accelerate custom instruction design: An RVV extension, inspired by a ByteDance proposal, designed to accelerate video codec processing. An RVV extension optimized for element-wise kernel functions frequently used in AI workloads.
ChingChe Yen
Software Engineer, Andes Technology
11:10 - 11:30 Leveraging Transaction-Based Acceleration for High-Speed, High-Quality RISC-V Verification Leveraging Transaction-Based Acceleration for High-Speed, High-Quality RISC-V Verification The RISC-V Verification Interface (RVVI) provides a standardized framework for ensuring Instruction Set Architecture (ISA) compliance and functional correctness in RISC-V cores. However, as designs scale in complexity with custom extensions, RVVI’s reliance on traditional simulation-based verification becomes a bottleneck- limiting execution speed, debug visibility, and scalability for system-level validation.
This paper outlines how applying Transaction-Based Acceleration (TBA) techniques augments RVVI to overcome these challenges, enabling high-speed, high-quality verification through co-emulation between Virtual Platforms (e.g., S2C Genesis) and hardware emulators (e.g., S2C OmniArk). By decoupling RVVI’s test scenarios into reusable transaction streams, we demonstrate how TBA preserves RVVI’s compliance checks while accelerating system-level validation. 		Leveraging Transaction-Based Acceleration for High-Speed, High-Quality RISC-V Verification Leveraging Transaction-Based Acceleration for High-Speed, High-Quality RISC-V Verification The RISC-V Verification Interface (RVVI) provides a standardized framework for ensuring Instruction Set Architecture (ISA) compliance and functional correctness in RISC-V cores. However, as designs scale in complexity with custom extensions, RVVI’s reliance on traditional simulation-based verification becomes a bottleneck- limiting execution speed, debug visibility, and scalability for system-level validation.
This paper outlines how applying Transaction-Based Acceleration (TBA) techniques augments RVVI to overcome these challenges, enabling high-speed, high-quality verification through co-emulation between Virtual Platforms (e.g., S2C Genesis) and hardware emulators (e.g., S2C OmniArk). By decoupling RVVI’s test scenarios into reusable transaction streams, we demonstrate how TBA preserves RVVI’s compliance checks while accelerating system-level validation.
Dehao Yang
Senior Software Development Engineer, S2C
11:30 - 11:50 Test Generation for RISC-V HPC Verification Challenges Test Generation for RISC-V HPC Verification Challenges High performance RISC-V CPUs are gaining popularity thanks to the open-source, modular design of the RISC-V ISA. This enables the development of custom RISC-V processors targeting diverse application such as AI, edge computing, and data centers, and drives widespread adoption in both industry and academia. With the integration of Hypervisor and Vector extensions, RISC-V has become more suitable for high-performance computing. However, this also adds significant complexity and challenges to CPU design verification. Developers of high- performance RISC-V CPUs require special purpose design verification tools that can generate diverse and complex instruction sequences to test the robustness, correctness, and performance of their RISC-V implementation.
This presentation will highlight the challenges inherent to the design verification of high-performance RISC-V CPUs with an emphasis on the problem of test generation and checking. The requirements for a verification tool that addresses these challenges will be explained, with examples provided using RISC-V verification tools (STING and ImperasDV) from Synopsys. 		Test Generation for RISC-V HPC Verification Challenges Test Generation for RISC-V HPC Verification Challenges High performance RISC-V CPUs are gaining popularity thanks to the open-source, modular design of the RISC-V ISA. This enables the development of custom RISC-V processors targeting diverse application such as AI, edge computing, and data centers, and drives widespread adoption in both industry and academia. With the integration of Hypervisor and Vector extensions, RISC-V has become more suitable for high-performance computing. However, this also adds significant complexity and challenges to CPU design verification. Developers of high- performance RISC-V CPUs require special purpose design verification tools that can generate diverse and complex instruction sequences to test the robustness, correctness, and performance of their RISC-V implementation.
This presentation will highlight the challenges inherent to the design verification of high-performance RISC-V CPUs with an emphasis on the problem of test generation and checking. The requirements for a verification tool that addresses these challenges will be explained, with examples provided using RISC-V verification tools (STING and ImperasDV) from Synopsys.
Yujie Fan
Application Engineer, Synopsys
11:50 - 12:10 RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC Platforms RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC Platforms The advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general, these types of scenarios will become commonplace. This presentation will discuss a specific complex, but yet commonplace, verification challenge for any team working on a complex RISC-V core, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC. RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC Platforms RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC Platforms The advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general, these types of scenarios will become commonplace. This presentation will discuss a specific complex, but yet commonplace, verification challenge for any team working on a complex RISC-V core, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC.
Adnan Hamid
Founder and CTO, Breker Verification Systems
12:10 - 12:30 RISC-V Chip Design Solution Based on Open-Source IP and Open-Source EDA This presentation introduces a fully open-source RISC-V chip design solution built on open-source EDA tools, open-source IP, and open PDKs, supporting one-stop SoC design from specification definition to hardware-software system integration. The proposed solution breaks through the high costs and technical barriers of chip design through vertically integrated in-house EDA tools and mature open-source components.
The presentation will cover the current status of global open-source full-chain chip design; Key components of the solution, including reference chips, open-source interface IPs, the open-source EDA platform iEDA, the intelligent design framework AiEDA, and the cloud-native agile design platform; Application cases in university research, custom chips for small businesses, and the "One Student One Chip" project.
This open-source RISC-V chip design solution is expected to significantly reduce the cost of chip design prototyping, demonstrating the feasibility and scalability of open-source models in chip design. It provides a new pathway for the inclusive development of the RISC-V ecosystem. 		RISC-V Chip Design Solution Based on Open-Source IP and Open-Source EDA This presentation introduces a fully open-source RISC-V chip design solution built on open-source EDA tools, open-source IP, and open PDKs, supporting one-stop SoC design from specification definition to hardware-software system integration. The proposed solution breaks through the high costs and technical barriers of chip design through vertically integrated in-house EDA tools and mature open-source components.
The presentation will cover the current status of global open-source full-chain chip design; Key components of the solution, including reference chips, open-source interface IPs, the open-source EDA platform iEDA, the intelligent design framework AiEDA, and the cloud-native agile design platform; Application cases in university research, custom chips for small businesses, and the "One Student One Chip" project.
This open-source RISC-V chip design solution is expected to significantly reduce the cost of chip design prototyping, demonstrating the feasibility and scalability of open-source models in chip design. It provides a new pathway for the inclusive development of the RISC-V ecosystem.
Biwei Xie
Associate Professor, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)
Cutting-edge Technology Innovation
Host:
Jun Han, Professor, Fudan University; Director, IP & Architecture Innovation Center, National Key Lab of Integrated Chips and SystemsBo Huang, Distinguished Professor, School of Data Science and Engineering, East China Normal University
7/18 13:30-17:30
Room 302
Time Title SpeakerTitle & Speaker
13:30 - 13:50 Energy-Efficient Embodied Intelligence Computing Architecture and Chips Autonomous intelligent systems are emerging as a new driving force for the development of chip technology. The International Roadmap for Devices and Systems (IRDS) has consecutively released white papers on autonomous machine computing for two years (2022, 2023), explicitly pointing out that developing chips for future autonomous intelligent systems requires attention to the important direction of embodied intelligence – which introduces large models into robots, enabling them to possess environmental understanding and reasoning capabilities and continue learning through interaction, forming a continuously evolving technical architecture. Currently, there are three technical paradigms for embedding large models into robots: single-module end-to-end, multi-module end-to-end, and hybrid AI systems, while hybrid AI + heterogeneous computing, as an efficient technical route for embodied intelligence, can alleviate the dependence on extremely large models and computing power. Developing new heterogeneous processor cores oriented to the computing needs of embodied intelligence based on the RISC-V open instruction architecture is an important approach to constructing superheterogeneous autonomous intelligent systems, with key issues to be urgently addressed including on-chip self-learning architecture, efficient multi-modal large model inference, dedicated mapping and positioning architecture, dedicated motion planning architecture, and superheterogeneous resource mapping and process scheduling. Energy-Efficient Embodied Intelligence Computing Architecture and Chips Autonomous intelligent systems are emerging as a new driving force for the development of chip technology. The International Roadmap for Devices and Systems (IRDS) has consecutively released white papers on autonomous machine computing for two years (2022, 2023), explicitly pointing out that developing chips for future autonomous intelligent systems requires attention to the important direction of embodied intelligence – which introduces large models into robots, enabling them to possess environmental understanding and reasoning capabilities and continue learning through interaction, forming a continuously evolving technical architecture. Currently, there are three technical paradigms for embedding large models into robots: single-module end-to-end, multi-module end-to-end, and hybrid AI systems, while hybrid AI + heterogeneous computing, as an efficient technical route for embodied intelligence, can alleviate the dependence on extremely large models and computing power. Developing new heterogeneous processor cores oriented to the computing needs of embodied intelligence based on the RISC-V open instruction architecture is an important approach to constructing superheterogeneous autonomous intelligent systems, with key issues to be urgently addressed including on-chip self-learning architecture, efficient multi-modal large model inference, dedicated mapping and positioning architecture, dedicated motion planning architecture, and superheterogeneous resource mapping and process scheduling.
Hongbin Sun
Professor, Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University
13:50 - 14:10 RISC-V Secure Isolation via Hardware-Software Co-Design: a Case Study of Penglai RISC-V Secure Isolation via Hardware-Software Co-Design: a Case Study of Penglai With the emergence of new intelligent applications such as ChatGPT, Mobile Agents, and Recall, confidential computing on smart devices is receiving increasing attention. This presentation will introduce the new challenges posed by on-device intelligent applications in terms of data security, the resulting requirements for underlying system hardware and software, and our exploration and reflections on using the Penglai RISC-V TEE to protect intelligent applications. RISC-V Secure Isolation via Hardware-Software Co-Design: a Case Study of Penglai RISC-V Secure Isolation via Hardware-Software Co-Design: a Case Study of Penglai With the emergence of new intelligent applications such as ChatGPT, Mobile Agents, and Recall, confidential computing on smart devices is receiving increasing attention. This presentation will introduce the new challenges posed by on-device intelligent applications in terms of data security, the resulting requirements for underlying system hardware and software, and our exploration and reflections on using the Penglai RISC-V TEE to protect intelligent applications.
Yubin Xia
Professor, Shanghai Jiao Tong University
14:10 - 14:30 LLM-aided Agile Design Methodologies for RISC-V SoC LLM-aided Agile Design Methodologies for RISC-V SoC The rapid development of artificial intelligence requires energy-efficient AI SoC chips to meet the computing and energy limitations. This speech will introduce some innovative cases for RISC-V designs to achieve high energy efficiency and agile AI SoC design. For example, we explored LLM-aided agile design and optimization methods based on large language models, focusing on high-performance CPUs and domain specific custom SoCs for design space exploration, design code generation, SoC integration, etc. By exploring agile chip design methods, designers can significantly improve the computational energy efficiency and design speed of SoC chips. LLM-aided Agile Design Methodologies for RISC-V SoC LLM-aided Agile Design Methodologies for RISC-V SoC The rapid development of artificial intelligence requires energy-efficient AI SoC chips to meet the computing and energy limitations. This speech will introduce some innovative cases for RISC-V designs to achieve high energy efficiency and agile AI SoC design. For example, we explored LLM-aided agile design and optimization methods based on large language models, focusing on high-performance CPUs and domain specific custom SoCs for design space exploration, design code generation, SoC integration, etc. By exploring agile chip design methods, designers can significantly improve the computational energy efficiency and design speed of SoC chips.
Tianyu Jia
Assistant Professor, the School of Integrated Circuits, Peking University
14:30 - 14:50 Hardware Page Automated Design and Verification Based on Large Language Models Hardware Page Automated Design and Verification Based on Large Language Models With the breakthrough of artificial intelligence technology, the Large Language Model (LLM) is deeply empowering the entire process of processor design and verification, driving the evolution of chip development towards intelligence and efficiency.
This talk covers the research progress of big models for RISC-V processor design and verification, and looks forward to development trends: In the future, with the deepening of technologies such as domain adaptive training and multimodal data fusion, big models are expected to achieve full closed-loop autonomous design from demand input to tape-out verification, especially in the field of dedicated processors (such as NPU/GPU), or may be the first to break through the limits of human design: This change will reshape the chip industry ecosystem, lower the technical threshold for small and medium-sized enterprises, and accelerate the innovation and iteration of intelligent computing hardware. 		Hardware Page Automated Design and Verification Based on Large Language Models Hardware Page Automated Design and Verification Based on Large Language Models With the breakthrough of artificial intelligence technology, the Large Language Model (LLM) is deeply empowering the entire process of processor design and verification, driving the evolution of chip development towards intelligence and efficiency.
This talk covers the research progress of big models for RISC-V processor design and verification, and looks forward to development trends: In the future, with the deepening of technologies such as domain adaptive training and multimodal data fusion, big models are expected to achieve full closed-loop autonomous design from demand input to tape-out verification, especially in the field of dedicated processors (such as NPU/GPU), or may be the first to break through the limits of human design: This change will reshape the chip industry ecosystem, lower the technical threshold for small and medium-sized enterprises, and accelerate the innovation and iteration of intelligent computing hardware.
Di Zhao
Associate Professor, Institute of Computing Technology, Chinese Academy of Sciences
Honggang Qi
Professor, University of Chinese Academy of Sciences
14:50 - 15:10 Addressing Real-time Application Requirements with RISC-V Advanced Interrupt Architecture Extensions RISC-V provides a range of interrupt architecture,
targeting various applications. This includes Core Local Interrupter (CLINT) defined in the RISC-V Privileged ISA, RISC-V Advanced Interrupt Architecture (AIA), and application specific interrupt controllers for small real-time systems such as Core Local Interrupt Controller (CLIC). All interrupt architectures have architecture specific programming models, making it difficult to develop universal software and provide a proper virtual environment.
The most feature rich interrupt architecture available is the RISC-V ratified standard AIA. It supports single/multi-core designs including virtualization extensions. Major disadvantages of the AIA:
- Lack of real-time/safety features such as interrupt preemption, timing guaranties, high software overhead at interrupt enter/leave - Significant silicon area of external interrupt controller for single core designs This presentation describes proposed extensions to the RISC-V AIA tailored for real-time/safety applications and resource constrained systems, enabling high-end systems with real-time/safety requirements and low-end real-time embedded systems in virtualized environments. 		Addressing Real-time Application Requirements with RISC-V Advanced Interrupt Architecture Extensions RISC-V provides a range of interrupt architecture,
targeting various applications. This includes Core Local Interrupter (CLINT) defined in the RISC-V Privileged ISA, RISC-V Advanced Interrupt Architecture (AIA), and application specific interrupt controllers for small real-time systems such as Core Local Interrupt Controller (CLIC). All interrupt architectures have architecture specific programming models, making it difficult to develop universal software and provide a proper virtual environment.
The most feature rich interrupt architecture available is the RISC-V ratified standard AIA. It supports single/multi-core designs including virtualization extensions. Major disadvantages of the AIA:
- Lack of real-time/safety features such as interrupt preemption, timing guaranties, high software overhead at interrupt enter/leave - Significant silicon area of external interrupt controller for single core designs This presentation describes proposed extensions to the RISC-V AIA tailored for real-time/safety applications and resource constrained systems, enabling high-end systems with real-time/safety requirements and low-end real-time embedded systems in virtualized environments.
Rich Collins
Sr. Director, Product Management - ARC-V Processors and Ecosystem, Synopsys
15:10 - 15:40 Tea Break
Tea Break
15:40 - 16:00 Achieving Persistent Tagging for Robust Stack Memory Error Protection
Achieving Persistent Tagging for Robust Stack Memory Error Protection
Carlo Ramponi
PhD Security Researcher, University of Trento
16:00 - 16:20 Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads
Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads
Ella Mao
Staff Applications Engineer, Synopsys
16:20 - 16:40 Latest RISC-V Instruction for DSP and Innovation Application of DSA in the Field of Wireless Communication Latest RISC-V Instruction for DSP and Innovation Application of DSA in the Field of Wireless Communication This topic introduces the latest innovations in DSP based on the RISC-V RVV instruction set architecture, as well as its applications and achievements in the field of wireless communications. Currently, the Xcmvw instruction set has been adopted as the base reference for candidate RVV DSP TG . Additionally, it presents XVE (X Vector Engine, X means different application scenario), a near-memory computing architecture supporting the RISC-V instruction set, featuring an out-of-order vector processor design. The discussion highlights its applications in 5G communications and its advantages. This architecture is not only well-suited for wireless signal processing but also effectively supports neural network and LLM inference acceleration. Latest RISC-V Instruction for DSP and Innovation Application of DSA in the Field of Wireless Communication Latest RISC-V Instruction for DSP and Innovation Application of DSA in the Field of Wireless Communication This topic introduces the latest innovations in DSP based on the RISC-V RVV instruction set architecture, as well as its applications and achievements in the field of wireless communications. Currently, the Xcmvw instruction set has been adopted as the base reference for candidate RVV DSP TG . Additionally, it presents XVE (X Vector Engine, X means different application scenario), a near-memory computing architecture supporting the RISC-V instruction set, featuring an out-of-order vector processor design. The discussion highlights its applications in 5G communications and its advantages. This architecture is not only well-suited for wireless signal processing but also effectively supports neural network and LLM inference acceleration.
Gaoshan Li
Senior Expert, Chip Architecture Design, Xinsheng Technology
16:40 - 17:00 Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Embedded real-time systems impose rigorous timing constraints, where the failure to complete critical tasks within prescribed deadlines can lead to system crashes and catastrophic errors. Control latency, encompassing I/O and interrupt latency, significantly impacts system performance. Previous studies have primarily concentrated on architectural design to meet timing requirements or optimize for performance enhancement. This work introduces a deterministic response architecture called Sophon, founded on the open and freely available RISC-V instruction set. The essential part of this architecture is a tiny and flexible Sophon core with fixed instruction latency. An enhanced ISA extension interface capable of transmitting up to 32 operands in a single instruction is proposed, facilitating the development of domain-specific applications. Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Embedded real-time systems impose rigorous timing constraints, where the failure to complete critical tasks within prescribed deadlines can lead to system crashes and catastrophic errors. Control latency, encompassing I/O and interrupt latency, significantly impacts system performance. Previous studies have primarily concentrated on architectural design to meet timing requirements or optimize for performance enhancement. This work introduces a deterministic response architecture called Sophon, founded on the open and freely available RISC-V instruction set. The essential part of this architecture is a tiny and flexible Sophon core with fixed instruction latency. An enhanced ISA extension interface capable of transmitting up to 32 operands in a single instruction is proposed, facilitating the development of domain-specific applications.
Zhe Huang
Engineer, Peng Cheng Laboratory
17:00 - 17:15 High-Performance RISC-V SoC Architectures: Current Progress and Future Roadmap High-Performance RISC-V SoC Architectures: Current Progress and Future Roadmap With the growing adoption of RISC-V, its application scope has expanded from embedded devices like MCUs and AIoT to higher-tier domains such as desktop computing and high-performance computing (HPC). Recent years have witnessed an emergence of high-performance RISC-V processor IP cores, driving the need for synchronized evolution in SoC architectures to address challenges including bandwidth bottlenecks, virtualization support, and security solutions. This presentation will focus on:
1) State-of-the-Art High-Performance RISC-V SoCs
2) Technical Challenges in High-Performance RISC-V SoCs
3) Timeintelli's Cybertron: A High-Performance RISC-V SoC Platform
4) Future Roadmap for High-performance RISC-V SoC Architectures 		High-Performance RISC-V SoC Architectures: Current Progress and Future Roadmap High-Performance RISC-V SoC Architectures: Current Progress and Future Roadmap With the growing adoption of RISC-V, its application scope has expanded from embedded devices like MCUs and AIoT to higher-tier domains such as desktop computing and high-performance computing (HPC). Recent years have witnessed an emergence of high-performance RISC-V processor IP cores, driving the need for synchronized evolution in SoC architectures to address challenges including bandwidth bottlenecks, virtualization support, and security solutions. This presentation will focus on:
1) State-of-the-Art High-Performance RISC-V SoCs
2) Technical Challenges in High-Performance RISC-V SoCs
3) Timeintelli's Cybertron: A High-Performance RISC-V SoC Platform
4) Future Roadmap for High-performance RISC-V SoC Architectures
Xiaofei Ni
Head of R&D Center in Wuxi, Timesintelli Technology
17:15 - 17:30 Trends and Applications of Chiplet-Integrated Advanced Packaging Trends and Applications of Chiplet-Integrated Advanced Packaging With the explosive growth of RISC-V open source architecture, chip design faces complex challenges of multi-dimensional physical constraints. Traditional single field simulation can no longer meet the requirements of high performance, low power consumption and high reliability. This speech will explore how to accelerate RISC-V chip design and development through the deep integration of multi-physics field coupling simulation technology and the next-generation EDA tool chain. Trends and Applications of Chiplet-Integrated Advanced Packaging Trends and Applications of Chiplet-Integrated Advanced Packaging With the explosive growth of RISC-V open source architecture, chip design faces complex challenges of multi-dimensional physical constraints. Traditional single field simulation can no longer meet the requirements of high performance, low power consumption and high reliability. This speech will explore how to accelerate RISC-V chip design and development through the deep integration of multi-physics field coupling simulation technology and the next-generation EDA tool chain.
Wenliang Dai
Founder & CEO, Xpeedic
Investment and M&A
Host:
Lin Wang, Managing Partner, Walden InternationalFei Fei, General Manager, Shanghai Fortera Capital
7/18 9:00-12:00
Room 204
Time Title SpeakerTitle & Speaker
09:00 - 09:05 Opening Remarks
Opening Remarks
09:05 - 09:10 Forum Chairperson Remarks
Forum Chairperson Remarks
09:10 - 09:30 Sharing on the Investment Ecosystem Layout of RISC-V Industry
Sharing on the Investment Ecosystem Layout of RISC-V Industry
Fei Fei
General Manager, Fortera Capital
09:30 - 09:50 Current Situation and Outlook of Investment and Mergers & Acquisitions in the Chip Design Industry
Current Situation and Outlook of Investment and Mergers & Acquisitions in the Chip Design Industry
Yuwang Sun
Partner President, China Forture-Tech Capital
09:50 - 10:10 Some Thoughts on the Integration Trends and Transaction Practices in the Chip Industry
Some Thoughts on the Integration Trends and Transaction Practices in the Chip Industry
Zhiang Jiang
Head of Strategic Planning, Investment and M&A, 3peak
10:10 - 10:30 Overview and Trends of the Recent A-Share M&A and Restructuring Market
Overview and Trends of the Recent A-Share M&A and Restructuring Market
Di Zuo
Managing Director, Huatai United Securities
10:30 - 11:00 Tea Break
Tea Break
11:00 - 11:30 Panel Discussion I: Bridge of Eco-Finance
Panel Discussion I: Bridge of Eco-Finance
Moderator: Haisheng Zhao
Panelist: Lingrui Zhixin, Spacemit, WingSemi Technology, Walden International, China Construction Bank, Stock Equity
11:30 - 12:00 Panel Discussion II: Decoding Mergers and Acquisitions Targets
Panel Discussion II: Decoding Mergers and Acquisitions Targets
Moderator: Haisheng Zhao
Panelist: VeriSilicon, Brite Semiconductor, Southchip, Giantec, Telink, UNIVISTA, Zhangjiang Hi-Tech
Education & Talent Development
Host:
Pingqiang Zhou, Vice Dean & Professor, School of Information Science and Technology, ShanghaiTech UniversityXiaojun Guo, Executive Vice Dean, School of Integrated Circuits, Shanghai Jiao Tong University
7/18 13:30-17:30
Room 204
Time Title SpeakerTitle & Speaker
13:30 - 13:50 "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC One Student One Chip Initiative: Learn to Build RISC-V Chips from Scratch with MOOC The "One Student One Chip" Initiative will guide students to design a RISC-V processor chip from scratch, run their own system software and real program, and perform physical design through open-source EDA tools. The learning content covers the full-stack abstraction layer of the computer system, from applications, runtime environments, simple OS, ISA, to processor micro-architecture design, RTL coding, synthesis, place-and-route, timing analysis, and finally the generation of GDSII files. This report will introduce "One Student One Chip" Initiative from the teaching aspect, explain how to guide students to understand the relationship between each abstraction layer . "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC One Student One Chip Initiative: Learn to Build RISC-V Chips from Scratch with MOOC The "One Student One Chip" Initiative will guide students to design a RISC-V processor chip from scratch, run their own system software and real program, and perform physical design through open-source EDA tools. The learning content covers the full-stack abstraction layer of the computer system, from applications, runtime environments, simple OS, ISA, to processor micro-architecture design, RTL coding, synthesis, place-and-route, timing analysis, and finally the generation of GDSII files. This report will introduce "One Student One Chip" Initiative from the teaching aspect, explain how to guide students to understand the relationship between each abstraction layer .
Zihao Yu
PhD, Institute of Computing Technology, Chinese Academy of Sciences
Engineer, Beijing Institute of Open Source Chip
13:50 - 14:10 Teaching Computer Architecture and AI Accelerator Design through the RISC-V Ecosystem Teaching Computer Architecture and AI Accelerator Design through the RISC-V Ecosystem This talk presents a pedagogical framework utilizing the RISC-V Instruction Set Architecture to teach fundamental and advanced concepts in computer architecture, the development of embedded systems, large-scale digital integrated circuit design, with a specific focus on AI accelerators. RISC-V's modularity, simplicity, and openness provide an unparalleled platform for hands-on learning, enabling students to traverse the entire stack from instruction set definition down to RTL implementation. The curriculum integrates core computer architecture principles with practical large-scale digital design methodologies for complex digital systems. Crucially, it extends into the domain of domain-specific architecture by guiding students through the design, implementation, and optimization of custom AI accelerator cores tailored to specific workloads, exploiting RISC-V's extensibility. By bridging theoretical concepts with concrete RISC-V-based projects, this approach equips students with the holistic understanding and practical skills necessary to innovate in the rapidly evolving fields of processor and specialized hardware design, particularly for artificial intelligence applications. Teaching Computer Architecture and AI Accelerator Design through the RISC-V Ecosystem Teaching Computer Architecture and AI Accelerator Design through the RISC-V Ecosystem This talk presents a pedagogical framework utilizing the RISC-V Instruction Set Architecture to teach fundamental and advanced concepts in computer architecture, the development of embedded systems, large-scale digital integrated circuit design, with a specific focus on AI accelerators. RISC-V's modularity, simplicity, and openness provide an unparalleled platform for hands-on learning, enabling students to traverse the entire stack from instruction set definition down to RTL implementation. The curriculum integrates core computer architecture principles with practical large-scale digital design methodologies for complex digital systems. Crucially, it extends into the domain of domain-specific architecture by guiding students through the design, implementation, and optimization of custom AI accelerator cores tailored to specific workloads, exploiting RISC-V's extensibility. By bridging theoretical concepts with concrete RISC-V-based projects, this approach equips students with the holistic understanding and practical skills necessary to innovate in the rapidly evolving fields of processor and specialized hardware design, particularly for artificial intelligence applications.
Siting Liu
Assistant Professor with the School of Information Science and Technology, ShanghaiTech University
14:10 - 14:30 Teaching and Practice Application of Embedded Systems Based on RISC-V Processor Teaching and Practice Application of Embedded Systems Based on RISC-V Processor The papers analyze the current situation of the embedded RISC-V processor market in China, shares the thoughts on the challenges faced by the popularization of RISC-V application and the adoption of embedded system course, and introduces the key content and authors' considerations for the update of "In-depth Understanding of RISC-V Program Development (Second Edition)". The paper briefly describes the characteristics of RISC-V processor architecture, introduces the teaching content of RISC-V processor in the course "Embedded Microprocessor System", compares the differences between RV32 and traditional Arm Cortex-M architecture, analyzes the problem of porting programs from Cortex-M to RV32, and discusses the method of NPU with RV64 SoC in embedded AI application. Teaching and Practice Application of Embedded Systems Based on RISC-V Processor Teaching and Practice Application of Embedded Systems Based on RISC-V Processor The papers analyze the current situation of the embedded RISC-V processor market in China, shares the thoughts on the challenges faced by the popularization of RISC-V application and the adoption of embedded system course, and introduces the key content and authors' considerations for the update of "In-depth Understanding of RISC-V Program Development (Second Edition)". The paper briefly describes the characteristics of RISC-V processor architecture, introduces the teaching content of RISC-V processor in the course "Embedded Microprocessor System", compares the differences between RV32 and traditional Arm Cortex-M architecture, analyzes the problem of porting programs from Cortex-M to RV32, and discusses the method of NPU with RV64 SoC in embedded AI application.
Jinlong Lin
Professor, the School of Software and Microelectronics, Peking University
Allan He
Secretary General, the Embedded Systems Association
Deputy Editor-in-Chief, Embedded Technology and Intelligent Systems Founder, BMR
14:30 - 14:50 Digital Logic and SoC Design Education Practice Integrating RISC-V Open Platform Digital Logic and SoC Design Education Practice Integrating RISC-V Open Platform With the rapid development of the RISC-V open-source platform, the field of SoC design is facing unprecedented opportunities and challenges. Against this backdrop, how to deeply integrate RISC-V technology into teaching practice has become the key to cultivating integrated circuit design talents who can meet the needs of the times. Based on the exploration and practice of Shanghai Jiao Tong University, this paper details the digital logic and SoC design curriculum system built around the RISC-V open-source platform, as well as the implementation effects of this system. Digital Logic and SoC Design Education Practice Integrating RISC-V Open Platform Digital Logic and SoC Design Education Practice Integrating RISC-V Open Platform With the rapid development of the RISC-V open-source platform, the field of SoC design is facing unprecedented opportunities and challenges. Against this backdrop, how to deeply integrate RISC-V technology into teaching practice has become the key to cultivating integrated circuit design talents who can meet the needs of the times. Based on the exploration and practice of Shanghai Jiao Tong University, this paper details the digital logic and SoC design curriculum system built around the RISC-V open-source platform, as well as the implementation effects of this system.
Yanan Sun
Associate Professor, School of Integrated Circuits, Shanghai Jiao Tong University
14:50 - 15:10 "Dongshan" RISC-V Talent Cultivation Program Dongshan RISC-V Talent Cultivation Program The "Dongshan" cluster is the world's first server cluster based on the RISC-V architecture. It comprises 6 cabinets housing a total of 6,144 cores. With a computing power of 476.8 TFLOPS and storage capacity of 126 TB.The team has published 160 work reports related to RISC-V on Zhihu (https://www.zhihu.com/people/dahogn), effectively supporting RISC-V ecosystem development.
Following thorough work summarization and preparation, we will launch the "Dongshan" RISC-V Talent Cultivation Plan at the 5th RISC-V Summit China (Shanghai). The plan aims to equip 8,000 students with RISC-V-related software and hardware technologies by 2030. Participants will complete one comprehensive practical course and participate in one academic competition. Currently, preliminary preparations for the first batch of 1,000 MikeV Duo RISC-V development boards, donated to the incoming Shandong University Class of 2025 freshmen, have been completed. The team is actively designing the introductory materials (including little games), practical courses, and organizing corresponding competitions. 		"Dongshan" RISC-V Talent Cultivation Program Dongshan RISC-V Talent Cultivation Program The "Dongshan" cluster is the world's first server cluster based on the RISC-V architecture. It comprises 6 cabinets housing a total of 6,144 cores. With a computing power of 476.8 TFLOPS and storage capacity of 126 TB.The team has published 160 work reports related to RISC-V on Zhihu (https://www.zhihu.com/people/dahogn), effectively supporting RISC-V ecosystem development.
Following thorough work summarization and preparation, we will launch the "Dongshan" RISC-V Talent Cultivation Plan at the 5th RISC-V Summit China (Shanghai). The plan aims to equip 8,000 students with RISC-V-related software and hardware technologies by 2030. Participants will complete one comprehensive practical course and participate in one academic competition. Currently, preliminary preparations for the first batch of 1,000 MikeV Duo RISC-V development boards, donated to the incoming Shandong University Class of 2025 freshmen, have been completed. The team is actively designing the introductory materials (including little games), practical courses, and organizing corresponding competitions.
Hongjun Dai
Professor, Academy of Intelligent Innovation and School of Software, Shandong University
15:10 - 15:30 Teaching Practice of RISC-V Processor and DFT Technology for Postgraduates Teaching Practice of RISC-V Processor and DFT Technology for Postgraduates As RISC-V drives semiconductor innovation, the industry faces a critical shortage of Design-for-Testability (DFT) professionals. This presentation showcases a postgraduate course that equips students with practical DFT skills tailored to RISC-V processors.
The course focuses on guiding students through the entire DFT design process. Students learn to develop customized DFT solutions. They practice inserting scan chains into RTL code, optimizing test structures to reduce test time and hardware overhead, and generating test vectors for testing.
Test coverage analysis is a core component of the curriculum. Using simulations, students conduct fault injection experiments to measure and improve the effectiveness of DFT designs.
The course integrates real-world case studies from industry partnerships to expose students to practical challenges in RISC-V chip development. By the end of the course, students can create comprehensive DFT plans for RISC-V processors, bridging academic knowledge with industrial requirements. This teaching approach aims to address the talent gap in RISC-V DFT and provides actionable insights for universities to strengthen their specialized curriculum. 		Teaching Practice of RISC-V Processor and DFT Technology for Postgraduates Teaching Practice of RISC-V Processor and DFT Technology for Postgraduates As RISC-V drives semiconductor innovation, the industry faces a critical shortage of Design-for-Testability (DFT) professionals. This presentation showcases a postgraduate course that equips students with practical DFT skills tailored to RISC-V processors.
The course focuses on guiding students through the entire DFT design process. Students learn to develop customized DFT solutions. They practice inserting scan chains into RTL code, optimizing test structures to reduce test time and hardware overhead, and generating test vectors for testing.
Test coverage analysis is a core component of the curriculum. Using simulations, students conduct fault injection experiments to measure and improve the effectiveness of DFT designs.
The course integrates real-world case studies from industry partnerships to expose students to practical challenges in RISC-V chip development. By the end of the course, students can create comprehensive DFT plans for RISC-V processors, bridging academic knowledge with industrial requirements. This teaching approach aims to address the talent gap in RISC-V DFT and provides actionable insights for universities to strengthen their specialized curriculum.
Feng Liang
Professor, School of Microelectronics, Xi'an Jiaotong University
15:30 - 16:00 Tea Break
Tea Break
16:00 - 16:20 Educational Solutions and Early Practices Based on RISC-V Educational Solutions and Early Practices Based on RISC-V This presentation introduces a range of educational solutions, resources, and practical cases developed by StarFive through the integration of RISC-V, AI, OpenHarmony, and other emerging technologies. These include a "Tech Campus" program for primary and secondary schools, two RISC-V-based university courses (one in embedded development and the other in chip design), and development kits designed for real-world application development. Educational Solutions and Early Practices Based on RISC-V Educational Solutions and Early Practices Based on RISC-V This presentation introduces a range of educational solutions, resources, and practical cases developed by StarFive through the integration of RISC-V, AI, OpenHarmony, and other emerging technologies. These include a "Tech Campus" program for primary and secondary schools, two RISC-V-based university courses (one in embedded development and the other in chip design), and development kits designed for real-world application development.
Spark Fan
Sales Director, StarFive Technologies
16:20 - 16:40 RISC-V Software Development and VESC Introduction RISC-V Software Development and VESC Introduction VeriSilicon has developed a lot of SoCs base with RISC-V cores, including IoT platforms with BLE support, AI platforms with RISC-V & AI cores, automotive SoCs and high performance SoCs. The session introduces software training, software development experiments, and software function development based on the RISC-V platforms, The session also introduces the VeriSilicon Embedded Software Competition(VESC) to promote RISC-V and encourage college students to learn RISC-V software development. RISC-V Software Development and VESC Introduction RISC-V Software Development and VESC Introduction VeriSilicon has developed a lot of SoCs base with RISC-V cores, including IoT platforms with BLE support, AI platforms with RISC-V & AI cores, automotive SoCs and high performance SoCs. The session introduces software training, software development experiments, and software function development based on the RISC-V platforms, The session also introduces the VeriSilicon Embedded Software Competition(VESC) to promote RISC-V and encourage college students to learn RISC-V software development.
Alex Lin
Software Director, VeriSilicon
16:40 - 17:30 Panel Discussion: Co-creation, Sharing and Co-cultivate: Open Source "RISC-V Introduction" Courseware Empowers a New Talent Training Ecosystem in Universities Panel Discussion: Co-creation, Sharing and Co-cultivate: Open Source "RISC-V Introduction" Courseware Empowers a New Talent Training Ecosystem in Universities
Moderator: Wayne Dai
Chairman, SOPIC
Panelist:
Bob Hu
Founder, Nuclei
Jiangang Duan
Senior Advisor, SOPIC
Zhuo Zou
Professor, School of Information Science and Technology, Fudan University
Yanan Sun
Associate Professor, School of Integrated Circuits, Shanghai Jiao Tong University
Rui Zhang
Senior Engineer, College of Computer Science and Artificial Intelligence, Fudan University Deputy director of National Demonstration Center for Experimental Computer Education
Feng Liang
Professor, School of Microelectronics, Xi'an Jiaotong University
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